drivers/fpga/dfl.h
Source file repositories/reference/linux-study-clean/drivers/fpga/dfl.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/fpga/dfl.h- Extension
.h- Size
- 18418 bytes
- Lines
- 585
- Domain
- Driver Families
- Bucket
- drivers/fpga
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitfield.hlinux/cdev.hlinux/delay.hlinux/dfl.hlinux/eventfd.hlinux/fs.hlinux/interrupt.hlinux/iopoll.hlinux/io-64-nonatomic-lo-hi.hlinux/mod_devicetable.hlinux/platform_device.hlinux/slab.hlinux/uuid.hlinux/fpga/fpga-region.h
Detected Declarations
struct dfl_feature_dev_datastruct dfl_fpga_port_opsstruct dfl_feature_idstruct dfl_feature_driverstruct dfl_feature_irq_ctxstruct dfl_featurestruct dfl_feature_dev_datastruct dfl_feature_platform_datastruct dfl_feature_opsstruct dfl_fpga_enum_infostruct dfl_fpga_enum_dflstruct dfl_fpga_cdevfunction dfl_feature_dev_use_beginfunction dfl_feature_dev_use_endfunction dfl_feature_dev_use_countfunction dfl_fpga_fdata_set_privatefunction dfl_fpga_inode_to_feature_dev_datafunction dfl_get_feature_by_idfunction dfl_get_feature_ioaddr_by_idfunction to_dfl_feature_dev_datafunction dfl_feature_is_fmefunction dfl_feature_is_portfunction dfl_feature_revisionfunction dfl_fpga_cdev_find_port_data
Annotated Snippet
const struct file_operations *fops,
struct module *owner);
void dfl_fpga_dev_ops_unregister(struct platform_device *pdev);
static inline struct dfl_feature_dev_data *
dfl_fpga_inode_to_feature_dev_data(struct inode *inode)
{
struct dfl_feature_platform_data *pdata;
pdata = container_of(inode->i_cdev, struct dfl_feature_platform_data,
cdev);
return pdata->fdata;
}
#define dfl_fpga_dev_for_each_feature(fdata, feature) \
for ((feature) = (fdata)->features; \
(feature) < (fdata)->features + (fdata)->num; (feature)++)
static inline struct dfl_feature *
dfl_get_feature_by_id(struct dfl_feature_dev_data *fdata, u16 id)
{
struct dfl_feature *feature;
dfl_fpga_dev_for_each_feature(fdata, feature)
if (feature->id == id)
return feature;
return NULL;
}
static inline void __iomem *
dfl_get_feature_ioaddr_by_id(struct dfl_feature_dev_data *fdata, u16 id)
{
struct dfl_feature *feature = dfl_get_feature_by_id(fdata, id);
if (feature && feature->ioaddr)
return feature->ioaddr;
WARN_ON(1);
return NULL;
}
static inline struct dfl_feature_dev_data *
to_dfl_feature_dev_data(struct device *dev)
{
struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
return pdata->fdata;
}
static inline
struct device *dfl_fpga_fdata_to_parent(struct dfl_feature_dev_data *fdata)
{
return fdata->dev->dev.parent->parent;
}
static inline bool dfl_feature_is_fme(void __iomem *base)
{
u64 v = readq(base + DFH);
return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_FME);
}
static inline bool dfl_feature_is_port(void __iomem *base)
{
u64 v = readq(base + DFH);
return (FIELD_GET(DFH_TYPE, v) == DFH_TYPE_FIU) &&
(FIELD_GET(DFH_ID, v) == DFH_ID_FIU_PORT);
}
static inline u8 dfl_feature_revision(void __iomem *base)
{
return (u8)FIELD_GET(DFH_REVISION, readq(base + DFH));
}
/**
* struct dfl_fpga_enum_info - DFL FPGA enumeration information
*
* @dev: parent device.
* @dfls: list of device feature lists.
* @nr_irqs: number of irqs for all feature devices.
* @irq_table: Linux IRQ numbers for all irqs, indexed by hw irq numbers.
*/
struct dfl_fpga_enum_info {
struct device *dev;
struct list_head dfls;
unsigned int nr_irqs;
int *irq_table;
Annotation
- Immediate include surface: `linux/bitfield.h`, `linux/cdev.h`, `linux/delay.h`, `linux/dfl.h`, `linux/eventfd.h`, `linux/fs.h`, `linux/interrupt.h`, `linux/iopoll.h`.
- Detected declarations: `struct dfl_feature_dev_data`, `struct dfl_fpga_port_ops`, `struct dfl_feature_id`, `struct dfl_feature_driver`, `struct dfl_feature_irq_ctx`, `struct dfl_feature`, `struct dfl_feature_dev_data`, `struct dfl_feature_platform_data`, `struct dfl_feature_ops`, `struct dfl_fpga_enum_info`.
- Atlas domain: Driver Families / drivers/fpga.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.