drivers/fpga/xilinx-core.c

Source file repositories/reference/linux-study-clean/drivers/fpga/xilinx-core.c

File Facts

System
Linux kernel
Corpus path
drivers/fpga/xilinx-core.c
Extension
.c
Size
5671 bytes
Lines
230
Domain
Driver Families
Bucket
drivers/fpga
Inferred role
Driver Families: exported/initcall integration point
Status
integration implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

while (time_before(jiffies, timeout)) {
			int ret = gpiod_get_value(core->init_b);

			if (ret == value)
				return 0;

			if (ret < 0) {
				dev_err(&mgr->dev,
					"Error reading INIT_B (%d)\n", ret);
				return ret;
			}

			usleep_range(100, 400);
		}

		dev_err(&mgr->dev, "Timeout waiting for INIT_B to %s\n",
			value ? "assert" : "deassert");
		return -ETIMEDOUT;
	}

	udelay(alt_udelay);

	return 0;
}

static int xilinx_core_write_init(struct fpga_manager *mgr,
				  struct fpga_image_info *info, const char *buf,
				  size_t count)
{
	struct xilinx_fpga_core *core = mgr->priv;
	int err;

	if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) {
		dev_err(&mgr->dev, "Partial reconfiguration not supported\n");
		return -EINVAL;
	}

	gpiod_set_value(core->prog_b, 1);

	err = wait_for_init_b(mgr, 1, 1); /* min is 500 ns */
	if (err) {
		gpiod_set_value(core->prog_b, 0);
		return err;
	}

	gpiod_set_value(core->prog_b, 0);

	err = wait_for_init_b(mgr, 0, 0);
	if (err)
		return err;

	if (get_done_gpio(mgr)) {
		dev_err(&mgr->dev, "Unexpected DONE pin state...\n");
		return -EIO;
	}

	/* program latency */
	usleep_range(7500, 7600);
	return 0;
}

static int xilinx_core_write(struct fpga_manager *mgr, const char *buf,
			     size_t count)
{
	struct xilinx_fpga_core *core = mgr->priv;

	return core->write(core, buf, count);
}

static int xilinx_core_write_complete(struct fpga_manager *mgr,
				      struct fpga_image_info *info)
{
	struct xilinx_fpga_core *core = mgr->priv;
	unsigned long timeout =
		jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
	bool expired = false;
	int done;
	int ret;
	const char padding[1] = { 0xff };

	/*
	 * This loop is carefully written such that if the driver is
	 * scheduled out for more than 'timeout', we still check for DONE
	 * before giving up and we apply 8 extra CCLK cycles in all cases.
	 */
	while (!expired) {
		expired = time_after(jiffies, timeout);

		done = get_done_gpio(mgr);
		if (done < 0)

Annotation

Implementation Notes