drivers/fpga/zynqmp-fpga.c
Source file repositories/reference/linux-study-clean/drivers/fpga/zynqmp-fpga.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/fpga/zynqmp-fpga.c- Extension
.c- Size
- 3234 bytes
- Lines
- 145
- Domain
- Driver Families
- Bucket
- drivers/fpga
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dma-mapping.hlinux/fpga/fpga-mgr.hlinux/io.hlinux/kernel.hlinux/module.hlinux/of_address.hlinux/string.hlinux/firmware/xlnx-zynqmp.h
Detected Declarations
struct zynqmp_fpga_privfunction zynqmp_fpga_ops_write_initfunction zynqmp_fpga_ops_writefunction zynqmp_fpga_ops_statefunction status_showfunction zynqmp_fpga_probe
Annotated Snippet
struct zynqmp_fpga_priv {
struct device *dev;
u32 flags;
};
static int zynqmp_fpga_ops_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
const char *buf, size_t size)
{
struct zynqmp_fpga_priv *priv;
priv = mgr->priv;
priv->flags = info->flags;
return 0;
}
static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
const char *buf, size_t size)
{
struct zynqmp_fpga_priv *priv;
dma_addr_t dma_addr;
u32 eemi_flags = 0;
char *kbuf;
int ret;
priv = mgr->priv;
kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
if (!kbuf)
return -ENOMEM;
memcpy(kbuf, buf, size);
wmb(); /* ensure all writes are done before initiate FW call */
if (priv->flags & FPGA_MGR_PARTIAL_RECONFIG)
eemi_flags |= XILINX_ZYNQMP_PM_FPGA_PARTIAL;
ret = zynqmp_pm_fpga_load(dma_addr, size, eemi_flags);
dma_free_coherent(priv->dev, size, kbuf, dma_addr);
return ret;
}
static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
{
u32 status = 0;
zynqmp_pm_fpga_get_status(&status);
if (status & IXR_FPGA_DONE_MASK)
return FPGA_MGR_STATE_OPERATING;
return FPGA_MGR_STATE_UNKNOWN;
}
static ssize_t status_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
u32 status;
int ret;
ret = zynqmp_pm_fpga_get_config_status(&status);
if (ret)
return ret;
return sysfs_emit(buf, "0x%x\n", status);
}
static DEVICE_ATTR_RO(status);
static struct attribute *zynqmp_fpga_attrs[] = {
&dev_attr_status.attr,
NULL,
};
ATTRIBUTE_GROUPS(zynqmp_fpga);
static const struct fpga_manager_ops zynqmp_fpga_ops = {
.state = zynqmp_fpga_ops_state,
.write_init = zynqmp_fpga_ops_write_init,
.write = zynqmp_fpga_ops_write,
};
static int zynqmp_fpga_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct zynqmp_fpga_priv *priv;
struct fpga_manager *mgr;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
Annotation
- Immediate include surface: `linux/dma-mapping.h`, `linux/fpga/fpga-mgr.h`, `linux/io.h`, `linux/kernel.h`, `linux/module.h`, `linux/of_address.h`, `linux/string.h`, `linux/firmware/xlnx-zynqmp.h`.
- Detected declarations: `struct zynqmp_fpga_priv`, `function zynqmp_fpga_ops_write_init`, `function zynqmp_fpga_ops_write`, `function zynqmp_fpga_ops_state`, `function status_show`, `function zynqmp_fpga_probe`.
- Atlas domain: Driver Families / drivers/fpga.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.