drivers/fwctl/mlx5/main.c

Source file repositories/reference/linux-study-clean/drivers/fwctl/mlx5/main.c

File Facts

System
Linux kernel
Corpus path
drivers/fwctl/mlx5/main.c
Extension
.c
Size
12723 bytes
Lines
419
Domain
Driver Families
Bucket
drivers/fwctl
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mlx5ctl_uctx {
	struct fwctl_uctx uctx;
	u32 uctx_caps;
	u32 uctx_uid;
};

struct mlx5ctl_dev {
	struct fwctl_device fwctl;
	struct mlx5_core_dev *mdev;
};
DEFINE_FREE(mlx5ctl, struct mlx5ctl_dev *, if (_T) fwctl_put(&_T->fwctl));

struct mlx5_ifc_mbox_in_hdr_bits {
	u8 opcode[0x10];
	u8 uid[0x10];

	u8 reserved_at_20[0x10];
	u8 op_mod[0x10];

	u8 reserved_at_40[0x40];
};

struct mlx5_ifc_mbox_out_hdr_bits {
	u8 status[0x8];
	u8 reserved_at_8[0x18];

	u8 syndrome[0x20];

	u8 reserved_at_40[0x40];
};

enum {
	MLX5_UCTX_OBJECT_CAP_TOOLS_RESOURCES = 0x4,
};

enum {
	MLX5_CMD_OP_QUERY_DRIVER_VERSION = 0x10c,
	MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e,
	MLX5_CMD_OP_QUERY_RDB = 0x512,
	MLX5_CMD_OP_QUERY_PSV = 0x602,
	MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716,
	MLX5_CMD_OP_QUERY_NVMF_BACKEND_CONTROLLER = 0x722,
	MLX5_CMD_OP_QUERY_NVMF_NAMESPACE_CONTEXT = 0x728,
	MLX5_CMD_OP_QUERY_ADJACENT_FUNCTIONS_ID = 0x730,
	MLX5_CMD_OP_DELEGATE_VHCA_MANAGEMENT = 0x731,
	MLX5_CMD_OP_QUERY_DELEGATED_VHCA = 0x732,
	MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813,
	MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS = 0x819,
	MLX5_CMD_OP_SET_DIAGNOSTIC_PARAMS = 0x820,
	MLX5_CMD_OP_QUERY_DIAGNOSTIC_COUNTERS = 0x821,
	MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911,
	MLX5_CMD_OP_QUERY_AFU = 0x971,
	MLX5_CMD_OP_QUERY_CAPI_PEC = 0x981,
	MLX5_CMD_OP_QUERY_UCTX = 0xa05,
	MLX5_CMD_OP_QUERY_UMEM = 0xa09,
	MLX5_CMD_OP_QUERY_NVMF_CC_RESPONSE = 0xb02,
	MLX5_CMD_OP_QUERY_EMULATED_FUNCTIONS_INFO = 0xb03,
	MLX5_CMD_OP_QUERY_REGEXP_PARAMS = 0xb05,
	MLX5_CMD_OP_QUERY_REGEXP_REGISTER = 0xb07,
	MLX5_CMD_OP_USER_QUERY_XRQ_DC_PARAMS_ENTRY = 0xb08,
	MLX5_CMD_OP_USER_QUERY_XRQ_ERROR_PARAMS = 0xb0a,
	MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
	MLX5_CMD_OP_QUERY_EMULATION_DEVICE_EQ_MSIX_MAPPING = 0xb0f,
	MLX5_CMD_OP_QUERY_MATCH_SAMPLE_INFO = 0xb13,
	MLX5_CMD_OP_QUERY_CRYPTO_STATE = 0xb14,
	MLX5_CMD_OP_QUERY_VUID = 0xb22,
	MLX5_CMD_OP_QUERY_DPA_PARTITION = 0xb28,
	MLX5_CMD_OP_QUERY_DPA_PARTITIONS = 0xb2a,
	MLX5_CMD_OP_POSTPONE_CONNECTED_QP_TIMEOUT = 0xb2e,
	MLX5_CMD_OP_QUERY_EMULATED_RESOURCES_INFO = 0xb2f,
	MLX5_CMD_OP_QUERY_RSV_RESOURCES = 0x8000,
	MLX5_CMD_OP_QUERY_MTT = 0x8001,
	MLX5_CMD_OP_QUERY_SCHED_QUEUE = 0x8006,
};

static int mlx5ctl_alloc_uid(struct mlx5ctl_dev *mcdev, u32 cap)
{
	u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {};
	u32 in[MLX5_ST_SZ_DW(create_uctx_in)] = {};
	void *uctx;
	int ret;
	u16 uid;

	uctx = MLX5_ADDR_OF(create_uctx_in, in, uctx);

	mlx5ctl_dbg(mcdev, "%s: caps 0x%x\n", __func__, cap);
	MLX5_SET(create_uctx_in, in, opcode, MLX5_CMD_OP_CREATE_UCTX);
	MLX5_SET(uctx, uctx, cap, cap);

	ret = mlx5_cmd_exec(mcdev->mdev, in, sizeof(in), out, sizeof(out));

Annotation

Implementation Notes