drivers/gpib/agilent_82350b/agilent_82350b.h

Source file repositories/reference/linux-study-clean/drivers/gpib/agilent_82350b/agilent_82350b.h

File Facts

System
Linux kernel
Corpus path
drivers/gpib/agilent_82350b/agilent_82350b.h
Extension
.h
Size
3199 bytes
Lines
158
Domain
Driver Families
Bucket
drivers/gpib
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct agilent_82350b_priv {
	struct tms9914_priv tms9914_priv;
	struct pci_dev *pci_device;
	void __iomem *plx_base;	/* 82350a only */
	void __iomem *gpib_base;
	void __iomem *sram_base;
	void __iomem *misc_base;
	void __iomem *borg_base;
	int irq;
	unsigned short card_mode_bits;
	unsigned short event_status_bits;
	enum board_model model;
	bool using_fifos;
};

/* registers */
enum agilent_82350b_gpib_registers

{
	CARD_MODE_REG = 0x1,
	CONFIG_DATA_REG = 0x2, /* 82350A specific */
	INTERRUPT_ENABLE_REG = 0x3,
	EVENT_STATUS_REG = 0x4,
	EVENT_ENABLE_REG = 0x5,
	STREAM_STATUS_REG = 0x7,
	DEBUG_RAM0_REG = 0x8,
	DEBUG_RAM1_REG = 0x9,
	DEBUG_RAM2_REG = 0xa,
	DEBUG_RAM3_REG = 0xb,
	XFER_COUNT_LO_REG = 0xc,
	XFER_COUNT_MID_REG = 0xd,
	XFER_COUNT_HI_REG = 0xe,
	TMS9914_BASE_REG = 0x10,
	INTERNAL_CONFIG_REG = 0x18,
	IMR0_READ_REG = 0x19, /* read */
	T1_DELAY_REG = 0x19, /* write */
	IMR1_READ_REG = 0x1a,
	ADR_READ_REG = 0x1b,
	SPMR_READ_REG = 0x1c,
	PPR_READ_REG = 0x1d,
	CDOR_READ_REG = 0x1e,
	SRAM_ACCESS_CONTROL_REG = 0x1f,
};

enum card_mode_bits

{
	ACTIVE_CONTROLLER_BIT = 0x2, /* read-only */
	CM_SYSTEM_CONTROLLER_BIT = 0x8,
	ENABLE_BUS_MONITOR_BIT = 0x10,
	ENABLE_PCI_IRQ_BIT = 0x20,
};

enum interrupt_enable_bits

{
	ENABLE_TMS9914_INTERRUPTS_BIT = 0x1,
	ENABLE_BUFFER_END_INTERRUPT_BIT = 0x10,
	ENABLE_TERM_COUNT_INTERRUPT_BIT = 0x20,
};

enum event_enable_bits

{
	ENABLE_BUFFER_END_EVENTS_BIT = 0x10,
	ENABLE_TERM_COUNT_EVENTS_BIT = 0x20,
};

enum event_status_bits

{
	TMS9914_IRQ_STATUS_BIT = 0x1,
	IRQ_STATUS_BIT = 0x2,
	BUFFER_END_STATUS_BIT = 0x10, /* write-clear */
	TERM_COUNT_STATUS_BIT = 0x20, /* write-clear */
};

enum stream_status_bits

{
	HALTED_STATUS_BIT = 0x1, /* read */
	RESTART_STREAM_BIT = 0x1, /* write */
};

enum internal_config_bits

{
	IC_SYSTEM_CONTROLLER_BIT = 0x80,
};

Annotation

Implementation Notes