drivers/gpib/fmh_gpib/fmh_gpib.h

Source file repositories/reference/linux-study-clean/drivers/gpib/fmh_gpib/fmh_gpib.h

File Facts

System
Linux kernel
Corpus path
drivers/gpib/fmh_gpib/fmh_gpib.h
Extension
.h
Size
4651 bytes
Lines
178
Domain
Driver Families
Bucket
drivers/gpib
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct fmh_priv {
	struct nec7210_priv nec7210_priv;
	struct resource *gpib_iomem_res;
	struct resource *write_transfer_counter_res;
	struct resource *dma_port_res;
	int irq;
	struct dma_chan *dma_channel;
	u8 *dma_buffer;
	int dma_buffer_size;
	int dma_burst_length;
	void __iomem *fifo_base;
	unsigned supports_fifo_interrupts : 1;
};

static inline int fmh_gpib_half_fifo_size(struct fmh_priv *priv)
{
	return priv->dma_burst_length;
}

// registers beyond the nec7210 register set
enum fmh_gpib_regs {
	EXT_STATUS_1_REG = 0x9,
	STATE1_REG = 0xc,
	ISR0_IMR0_REG = 0xe,
	BUS_STATUS_REG = 0xf
};

/* IMR0 -- Interrupt Mode Register 0 */
enum imr0_bits {
	ATN_INTERRUPT_ENABLE_BIT = 0x4,
	IFC_INTERRUPT_ENABLE_BIT = 0x8
};

/* ISR0 -- Interrupt Status Register 0 */
enum isr0_bits {
	ATN_INTERRUPT_BIT = 0x4,
	IFC_INTERRUPT_BIT = 0x8
};

enum state1_bits {
	SOURCE_HANDSHAKE_SIDS_BITS = 0x0, /* source idle state */
	SOURCE_HANDSHAKE_SGNS_BITS = 0x1, /* source generate state */
	SOURCE_HANDSHAKE_SDYS_BITS = 0x2, /* source delay state */
	SOURCE_HANDSHAKE_STRS_BITS = 0x5, /* source transfer state */
	SOURCE_HANDSHAKE_MASK = 0x7
};

enum fmh_gpib_auxmr_bits {
	AUX_I_REG = 0xe0,
};

enum aux_reg_i_bits {
	LOCAL_PPOLL_MODE_BIT = 0x4
};

enum ext_status_1_bits {
	DATA_IN_STATUS_BIT = 0x01,
	DATA_OUT_STATUS_BIT = 0x02,
	COMMAND_OUT_STATUS_BIT = 0x04,
	RFD_HOLDOFF_STATUS_BIT = 0x08,
	END_STATUS_BIT = 0x10
};

/* dma fifo reg and bits */
enum dma_fifo_regs {
	FIFO_DATA_REG = 0x0,
	FIFO_CONTROL_STATUS_REG = 0x1,
	FIFO_XFER_COUNTER_REG = 0x2,
	FIFO_MAX_BURST_LENGTH_REG = 0x3
};

enum fifo_data_bits {
	FIFO_DATA_EOI_FLAG = 0x100
};

enum fifo_control_bits {
	TX_FIFO_DMA_REQUEST_ENABLE = 0x0001,
	TX_FIFO_CLEAR = 0x0002,
	TX_FIFO_HALF_EMPTY_INTERRUPT_ENABLE = 0x0008,
	RX_FIFO_DMA_REQUEST_ENABLE = 0x0100,
	RX_FIFO_CLEAR = 0x0200,
	RX_FIFO_HALF_FULL_INTERRUPT_ENABLE = 0x0800
};

enum fifo_status_bits {
	TX_FIFO_EMPTY = 0x0001,
	TX_FIFO_FULL = 0x0002,
	TX_FIFO_HALF_EMPTY = 0x0004,
	TX_FIFO_HALF_EMPTY_INTERRUPT_IS_ENABLED = 0x0008,
	TX_FIFO_DMA_REQUEST_IS_ENABLED = 0x0010,

Annotation

Implementation Notes