drivers/gpib/hp_82341/hp_82341.h

Source file repositories/reference/linux-study-clean/drivers/gpib/hp_82341/hp_82341.h

File Facts

System
Linux kernel
Corpus path
drivers/gpib/hp_82341/hp_82341.h
Extension
.h
Size
4477 bytes
Lines
166
Domain
Driver Families
Bucket
drivers/gpib
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct hp_82341_priv {
	struct tms9914_priv tms9914_priv;
	unsigned int irq;
	unsigned short config_control_bits;
	unsigned short mode_control_bits;
	unsigned short event_status_bits;
	struct pnp_dev *pnp_dev;
	unsigned long iobase[4];
	unsigned long io_region_offset;
	enum hp_82341_hardware_version hw_version;
};

static const int hp_82341_region_iosize = 0x8;
static const int hp_82341_num_io_regions = 4;
static const int hp_82341_fifo_size = 0xffe;
static const int hp_82341c_firmware_length = 5764;
static const int hp_82341d_firmware_length = 5302;

// hp 82341 register offsets
enum hp_82341_region_0_registers {
	CONFIG_CONTROL_STATUS_REG = 0x0,
	MODE_CONTROL_STATUS_REG = 0x1,
	MONITOR_REG = 0x2,	// after initialization
	XILINX_DATA_REG = 0x2,	// before initialization, write only
	INTERRUPT_ENABLE_REG = 0x3,
	EVENT_STATUS_REG = 0x4,
	EVENT_ENABLE_REG = 0x5,
	STREAM_STATUS_REG = 0x7,
};

enum hp_82341_region_1_registers {
	ID0_REG = 0x2,
	ID1_REG = 0x3,
	TRANSFER_COUNT_LOW_REG = 0x4,
	TRANSFER_COUNT_MID_REG = 0x5,
	TRANSFER_COUNT_HIGH_REG = 0x6,
};

enum hp_82341_region_3_registers {
	BUFFER_PORT_LOW_REG = 0x0,
	BUFFER_PORT_HIGH_REG = 0x1,
	ID2_REG = 0x2,
	ID3_REG = 0x3,
	BUFFER_FLUSH_REG = 0x4,
	BUFFER_CONTROL_REG = 0x7
};

enum config_control_status_bits {
	IRQ_SELECT_MASK = 0x7,
	DMA_CONFIG_MASK = 0x18,
	ENABLE_DMA_CONFIG_BIT = 0x20,
	XILINX_READY_BIT = 0x40,	// read only
	DONE_PGL_BIT = 0x80
};

static inline unsigned int IRQ_SELECT_BITS(int irq)
{
	switch (irq) {
	case 3:
		return 0x3;
	case 5:
		return 0x2;
	case 7:
		return 0x1;
	case 9:
		return 0x0;
	case 10:
		return 0x7;
	case 11:
		return 0x6;
	case 12:
		return 0x5;
	case 15:
		return 0x4;
	default:
		return 0x0;
	}
};

enum mode_control_status_bits {
	SLOT8_BIT = 0x1,		// read only
	ACTIVE_CONTROLLER_BIT = 0x2,	// read only
	ENABLE_DMA_BIT = 0x4,
	SYSTEM_CONTROLLER_BIT = 0x8,
	MONITOR_BIT = 0x10,
	ENABLE_IRQ_CONFIG_BIT = 0x20,
	ENABLE_TI_STREAM_BIT = 0x40
};

enum monitor_bits {

Annotation

Implementation Notes