drivers/gpib/include/nec7210_registers.h

Source file repositories/reference/linux-study-clean/drivers/gpib/include/nec7210_registers.h

File Facts

System
Linux kernel
Corpus path
drivers/gpib/include/nec7210_registers.h
Extension
.h
Size
5393 bytes
Lines
219
Domain
Driver Families
Bucket
drivers/gpib
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _NEC7210_REGISTERS_H
#define _NEC7210_REGISTERS_H

enum nec7210_chipset {
	NEC7210,	// The original
	TNT4882,	// NI
	NAT4882,	// NI
	CB7210,		// measurement computing
	IOT7210,	// iotech
	IGPIB7210,	// Ines
	TNT5004,	// NI (minor differences to TNT4882)
};

/*
 * nec7210 register numbers (might need to be multiplied by
 * a board-dependent offset to get actually io address offset)
 */
// write registers
enum nec7210_write_regs {
	CDOR,	// command/data out
	IMR1,	// interrupt mask 1
	IMR2,	// interrupt mask 2
	SPMR,	// serial poll mode
	ADMR,	// address mode
	AUXMR,	// auxiliary mode
	ADR,	// address
	EOSR,	// end-of-string

	// nec7210 has 8 registers
	nec7210_num_registers = 8,
};

// read registers
enum nec7210_read_regs {
	DIR,	// data in
	ISR1,	// interrupt status 1
	ISR2,	// interrupt status 2
	SPSR,	// serial poll status
	ADSR,	// address status
	CPTR,	// command pass though
	ADR0,	// address 1
	ADR1,	// address 2
};

// bit definitions common to nec-7210 compatible registers

// ISR1: interrupt status register 1
enum isr1_bits {
	HR_DI = (1 << 0),
	HR_DO = (1 << 1),
	HR_ERR = (1 << 2),
	HR_DEC = (1 << 3),
	HR_END = (1 << 4),
	HR_DET = (1 << 5),
	HR_APT = (1 << 6),
	HR_CPT = (1 << 7),
};

// IMR1: interrupt mask register 1
enum imr1_bits {
	HR_DIIE = (1 << 0),
	HR_DOIE = (1 << 1),
	HR_ERRIE = (1 << 2),
	HR_DECIE = (1 << 3),
	HR_ENDIE = (1 << 4),
	HR_DETIE = (1 << 5),
	HR_APTIE = (1 << 6),
	HR_CPTIE = (1 << 7),
};

// ISR2, interrupt status register 2
enum isr2_bits {
	HR_ADSC = (1 << 0),
	HR_REMC = (1 << 1),
	HR_LOKC = (1 << 2),
	HR_CO = (1 << 3),
	HR_REM = (1 << 4),
	HR_LOK = (1 << 5),
	HR_SRQI = (1 << 6),
	HR_INT = (1 << 7),
};

// IMR2, interrupt mask register 2
enum imr2_bits {
	// all the bits in this register that enable interrupts
	IMR2_ENABLE_INTR_MASK = 0x4f,
	HR_ACIE = (1 << 0),
	HR_REMIE = (1 << 1),
	HR_LOKIE = (1 << 2),
	HR_COIE = (1 << 3),

Annotation

Implementation Notes