drivers/gpib/include/tnt4882_registers.h

Source file repositories/reference/linux-study-clean/drivers/gpib/include/tnt4882_registers.h

File Facts

System
Linux kernel
Corpus path
drivers/gpib/include/tnt4882_registers.h
Extension
.h
Size
5838 bytes
Lines
193
Domain
Driver Families
Bucket
drivers/gpib
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _TNT4882_REGISTERS_H
#define _TNT4882_REGISTERS_H

// tnt4882 register offsets
enum {
	ACCWR = 0x5,
	// offset of auxiliary command register in 9914 mode
	AUXCR = 0x6,
	INTRT = 0x7,
	// register number for auxiliary command register when swap bit is set (9914 mode)
	SWAPPED_AUXCR = 0xa,
	HSSEL = 0xd,	// handshake select register
	CNT2 = 0x9,
	CNT3 = 0xb,
	CFG = 0x10,
	SASR = 0x1b,
	IMR0 = 0x1d,
	IMR3 = 0x12,
	CNT0 = 0x14,
	CNT1 = 0x16,
	KEYREG = 0x17,	// key control register (7210 mode only)
	CSR = KEYREG,
	FIFOB = 0x18,
	FIFOA = 0x19,
	CCR = 0x1a,	// carry cycle register
	CMDR = 0x1c,	// command register
	TIMER = 0x1e,	// timer register

	STS1 = 0x10,	// T488 Status Register 1
	STS2 = 0x1c,	// T488 Status Register 2
	ISR0 = IMR0,
	ISR3 = 0x1a,	// T488 Interrupt Status Register 3
	BCR = 0x1f,	// bus control/status register
	BSR = BCR,
};

enum {
	tnt_pagein_offset = 0x11,
};

/*============================================================*/

/* TURBO-488 registers bit definitions */

enum bus_control_status_bits {
	BCSR_REN_BIT = 0x1,
	BCSR_IFC_BIT = 0x2,
	BCSR_SRQ_BIT = 0x4,
	BCSR_EOI_BIT = 0x8,
	BCSR_NRFD_BIT = 0x10,
	BCSR_NDAC_BIT = 0x20,
	BCSR_DAV_BIT = 0x40,
	BCSR_ATN_BIT = 0x80,
};

/* CFG -- Configuration Register (write only) */
enum cfg_bits {
	TNT_COMMAND = 0x80,	/* bytes are command bytes instead of data bytes
				 * (tnt4882 one-chip and newer only?)
				 */
	TNT_TLCHE = (1 << 6),	/* halt transfer on imr0, imr1, or imr2 interrupt */
	TNT_IN = (1 << 5),	/* transfer is GPIB read		 */
	TNT_A_B = (1 << 4),	/* order to use fifos 1=fifo A first(big endian),
				 * 0=fifo b first(little endian)
				 */
	TNT_CCEN = (1 << 3),	/* enable carry cycle		      */
	TNT_TMOE = (1 << 2),	/* enable CPU bus time limit	      */
	TNT_TIM_BYTN = (1 << 1),	/* tmot reg is: 1=125ns clocks, 0=num bytes */
	TNT_B_16BIT = (1 << 0),	/* 1=FIFO is 16-bit register, 0=8-bit */
};

/* CMDR -- Command Register */
enum cmdr_bits {
	CLRSC = 0x2,	/* clear the system controller bit */
	SETSC = 0x3,	/* set the system controller bit */
	GO = 0x4,	/* start fifos */
	STOP = 0x8,	/* stop fifos */
	RESET_FIFO = 0x10,	/* reset the FIFOs		*/
	SOFT_RESET = 0x22,	/* issue a software reset	*/
	HARD_RESET = 0x40	/* 500x only? */
};

/* HSSEL -- handshake select register (write only) */
enum hssel_bits {
	TNT_ONE_CHIP_BIT = 0x1,
	NODMA = 0x10,
	TNT_GO2SIDS_BIT = 0x20,
};

/* IMR0 -- Interrupt Mode Register 0 */

Annotation

Implementation Notes