drivers/gpib/ines/ines.h

Source file repositories/reference/linux-study-clean/drivers/gpib/ines/ines.h

File Facts

System
Linux kernel
Corpus path
drivers/gpib/ines/ines.h
Extension
.h
Size
4063 bytes
Lines
166
Domain
Driver Families
Bucket
drivers/gpib
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ines_priv {
	struct nec7210_priv nec7210_priv;
	struct pci_dev *pci_device;
	// base address for plx9052 pci chip
	unsigned long plx_iobase;
	// base address for amcc5920 pci chip
	unsigned long amcc_iobase;
	unsigned int irq;
	enum ines_pci_chip pci_chip_type;
	u8 extend_mode_bits;
};

/* inb/outb wrappers */
static inline unsigned int ines_inb(struct ines_priv *priv, unsigned int register_number)
{
	return inb(priv->nec7210_priv.iobase +
		   register_number * priv->nec7210_priv.offset);
}

static inline void ines_outb(struct ines_priv *priv, unsigned int value,
			     unsigned int register_number)
{
	outb(value, priv->nec7210_priv.iobase +
	     register_number * priv->nec7210_priv.offset);
}

enum ines_regs {
	// read
	FIFO_STATUS = 0x8,
	ISR3 = 0x9,
	ISR4 = 0xa,
	IN_FIFO_COUNT = 0x10,
	OUT_FIFO_COUNT = 0x11,
	EXTEND_STATUS = 0xf,

	// write
	XDMA_CONTROL = 0x8,
	IMR3 = ISR3,
	IMR4 = ISR4,
	IN_FIFO_WATERMARK = IN_FIFO_COUNT,
	OUT_FIFO_WATERMARK = OUT_FIFO_COUNT,
	EXTEND_MODE = 0xf,

	// read-write
	XFER_COUNT_LOWER = 0xb,
	XFER_COUNT_UPPER = 0xc,
	BUS_CONTROL_MONITOR = 0x13,
};

enum isr3_imr3_bits {
	HW_TIMEOUT_BIT = 0x1,
	XFER_COUNT_BIT = 0x2,
	CMD_RECEIVED_BIT = 0x4,
	TCT_RECEIVED_BIT = 0x8,
	IFC_ACTIVE_BIT = 0x10,
	ATN_ACTIVE_BIT = 0x20,
	FIFO_ERROR_BIT = 0x40,
};

enum isr4_imr4_bits {
	IN_FIFO_WATERMARK_BIT = 0x1,
	OUT_FIFO_WATERMARK_BIT = 0x2,
	IN_FIFO_FULL_BIT = 0x4,
	OUT_FIFO_EMPTY_BIT = 0x8,
	IN_FIFO_READY_BIT = 0x10,
	OUT_FIFO_READY_BIT = 0x20,
	IN_FIFO_EXIT_WATERMARK_BIT = 0x40,
	OUT_FIFO_EXIT_WATERMARK_BIT = 0x80,
};

enum extend_mode_bits {
	TR3_TRIG_ENABLE_BIT = 0x1,	// enable generation of trigger pulse T/R3 pin
	// clear message available status bit when chip writes byte with EOI true
	MAV_ENABLE_BIT = 0x2,
	EOS1_ENABLE_BIT = 0x4,		// enable eos register 1
	EOS2_ENABLE_BIT = 0x8,		// enable eos register 2
	EOIDIS_BIT = 0x10,		// disable EOI interrupt when doing rfd holdoff on end?
	XFER_COUNTER_ENABLE_BIT = 0x20,
	XFER_COUNTER_OUTPUT_BIT = 0x40,	// use counter for output, clear for input
	// when xfer counter hits 0, assert EOI on write or RFD holdoff on read
	LAST_BYTE_HANDLING_BIT = 0x80,
};

enum extend_status_bits {
	OUTPUT_MESSAGE_IN_PROGRESS_BIT = 0x1,
	SCSEL_BIT = 0x2,	// statue of SCSEL pin
	LISTEN_DISABLED = 0x4,
	IN_FIFO_EMPTY_BIT = 0x8,
	OUT_FIFO_FULL_BIT = 0x10,
};

Annotation

Implementation Notes