drivers/gpib/tnt4882/mite.h
Source file repositories/reference/linux-study-clean/drivers/gpib/tnt4882/mite.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpib/tnt4882/mite.h- Extension
.h- Size
- 6105 bytes
- Lines
- 235
- Domain
- Driver Families
- Bucket
- drivers/gpib
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/pci.h
Detected Declarations
struct mite_dma_chainstruct mite_structenum mite_registersenum MITE_IODWBSR_bitsfunction mite_irqfunction mite_device_id
Annotated Snippet
struct mite_dma_chain {
u32 count;
u32 addr;
u32 next;
};
struct mite_struct {
struct mite_struct *next;
int used;
struct pci_dev *pcidev;
unsigned long mite_phys_addr;
void __iomem *mite_io_addr;
unsigned long daq_phys_addr;
void __iomem *daq_io_addr;
int DMA_CheckNearEnd;
struct mite_dma_chain ring[MITE_RING_SIZE];
};
extern struct mite_struct *mite_devices;
extern inline unsigned int mite_irq(struct mite_struct *mite)
{
return mite->pcidev->irq;
};
extern inline unsigned int mite_device_id(struct mite_struct *mite)
{
return mite->pcidev->device;
};
void mite_init(void);
void mite_cleanup(void);
int mite_setup(struct mite_struct *mite);
void mite_unsetup(struct mite_struct *mite);
void mite_list_devices(void);
#define CHAN_OFFSET(x) (0x100 * (x))
/* DMA base for chan 0 is 0x500, chan 1 is 0x600 */
#define MITE_CHOR 0x500
#define CHOR_DMARESET BIT(31)
#define CHOR_SET_SEND_TC BIT(11)
#define CHOR_CLR_SEND_TC BIT(10)
#define CHOR_SET_LPAUSE BIT(9)
#define CHOR_CLR_LPAUSE BIT(8)
#define CHOR_CLRDONE BIT(7)
#define CHOR_CLRRB BIT(6)
#define CHOR_CLRLC BIT(5)
#define CHOR_FRESET BIT(4)
#define CHOR_ABORT BIT(3)
#define CHOR_STOP BIT(2)
#define CHOR_CONT BIT(1)
#define CHOR_START BIT(0)
#define CHOR_PON (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE)
#define MITE_CHCR 0x504
#define CHCR_SET_DMA_IE BIT(31)
#define CHCR_CLR_DMA_IE BIT(30)
#define CHCR_SET_LINKP_IE BIT(29)
#define CHCR_CLR_LINKP_IE BIT(28)
#define CHCR_SET_SAR_IE BIT(27)
#define CHCR_CLR_SAR_IE BIT(26)
#define CHCR_SET_DONE_IE BIT(25)
#define CHCR_CLR_DONE_IE BIT(24)
#define CHCR_SET_MRDY_IE BIT(23)
#define CHCR_CLR_MRDY_IE BIT(22)
#define CHCR_SET_DRDY_IE BIT(21)
#define CHCR_CLR_DRDY_IE BIT(20)
#define CHCR_SET_LC_IE BIT(19)
#define CHCR_CLR_LC_IE BIT(18)
#define CHCR_SET_CONT_RB_IE BIT(17)
#define CHCR_CLR_CONT_RB_IE BIT(16)
#define CHCR_FIFODIS BIT(15)
#define CHCR_FIFO_ON 0
#define CHCR_BURSTEN BIT(14)
#define CHCR_NO_BURSTEN 0
#define CHCR_NFTP(x) ((x) << 11)
#define CHCR_NFTP0 CHCR_NFTP(0)
#define CHCR_NFTP1 CHCR_NFTP(1)
#define CHCR_NFTP2 CHCR_NFTP(2)
#define CHCR_NFTP4 CHCR_NFTP(3)
#define CHCR_NFTP8 CHCR_NFTP(4)
#define CHCR_NFTP16 CHCR_NFTP(5)
#define CHCR_NETP(x) ((x) << 11)
#define CHCR_NETP0 CHCR_NETP(0)
#define CHCR_NETP1 CHCR_NETP(1)
Annotation
- Immediate include surface: `linux/pci.h`.
- Detected declarations: `struct mite_dma_chain`, `struct mite_struct`, `enum mite_registers`, `enum MITE_IODWBSR_bits`, `function mite_irq`, `function mite_device_id`.
- Atlas domain: Driver Families / drivers/gpib.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.