drivers/gpio/gpio-aspeed-sgpio.c

Source file repositories/reference/linux-study-clean/drivers/gpio/gpio-aspeed-sgpio.c

File Facts

System
Linux kernel
Corpus path
drivers/gpio/gpio-aspeed-sgpio.c
Extension
.c
Size
18711 bytes
Lines
708
Domain
Driver Families
Bucket
drivers/gpio
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct aspeed_sgpio_pdata {
	const u32 pin_mask;
	const struct aspeed_sgpio_llops *llops;
	const u32 cfg_offset;
};

struct aspeed_sgpio {
	struct gpio_chip chip;
	struct device *dev;
	struct clk *pclk;
	raw_spinlock_t lock;
	void __iomem *base;
	int irq;
	const struct aspeed_sgpio_pdata *pdata;
};

struct aspeed_sgpio_bank {
	u16    val_regs;
	u16    rdata_reg;
	u16    irq_regs;
	u16    tolerance_regs;
};

/*
 * Note: The "value" register returns the input value when the GPIO is
 *	 configured as an input.
 *
 *	 The "rdata" register returns the output value when the GPIO is
 *	 configured as an output.
 */
static const struct aspeed_sgpio_bank aspeed_sgpio_banks[] = {
	{
		.val_regs = 0x0000,
		.rdata_reg = 0x0070,
		.irq_regs = 0x0004,
		.tolerance_regs = 0x0018,
	},
	{
		.val_regs = 0x001C,
		.rdata_reg = 0x0074,
		.irq_regs = 0x0020,
		.tolerance_regs = 0x0034,
	},
	{
		.val_regs = 0x0038,
		.rdata_reg = 0x0078,
		.irq_regs = 0x003C,
		.tolerance_regs = 0x0050,
	},
	{
		.val_regs = 0x0090,
		.rdata_reg = 0x007C,
		.irq_regs = 0x0094,
		.tolerance_regs = 0x00A8,
	},
};

enum aspeed_sgpio_reg {
	reg_val,
	reg_rdata,
	reg_irq_enable,
	reg_irq_type0,
	reg_irq_type1,
	reg_irq_type2,
	reg_irq_status,
	reg_tolerance,
};

struct aspeed_sgpio_llops {
	void (*reg_bit_set)(struct aspeed_sgpio *gpio, unsigned int offset,
			    const enum aspeed_sgpio_reg reg, bool val);
	bool (*reg_bit_get)(struct aspeed_sgpio *gpio, unsigned int offset,
			    const enum aspeed_sgpio_reg reg);
	int (*reg_bank_get)(struct aspeed_sgpio *gpio, unsigned int offset,
			    const enum aspeed_sgpio_reg reg);
};

#define GPIO_VAL_VALUE      0x00
#define GPIO_IRQ_ENABLE     0x00
#define GPIO_IRQ_TYPE0      0x04
#define GPIO_IRQ_TYPE1      0x08
#define GPIO_IRQ_TYPE2      0x0C
#define GPIO_IRQ_STATUS     0x10

static void __iomem *aspeed_sgpio_g4_bank_reg(struct aspeed_sgpio *gpio,
					      const struct aspeed_sgpio_bank *bank,
					      const enum aspeed_sgpio_reg reg)
{
	switch (reg) {
	case reg_val:

Annotation

Implementation Notes