drivers/gpio/gpio-crystalcove.c
Source file repositories/reference/linux-study-clean/drivers/gpio/gpio-crystalcove.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpio/gpio-crystalcove.c- Extension
.c- Size
- 10105 bytes
- Lines
- 399
- Domain
- Driver Families
- Bucket
- drivers/gpio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bitops.hlinux/gpio/driver.hlinux/interrupt.hlinux/mfd/intel_soc_pmic.hlinux/module.hlinux/platform_device.hlinux/regmap.hlinux/seq_file.hlinux/string_choices.hlinux/types.h
Detected Declarations
struct crystalcove_gpioenum ctrl_registerfunction to_regfunction crystalcove_update_irq_maskfunction crystalcove_update_irq_ctrlfunction crystalcove_gpio_dir_infunction crystalcove_gpio_dir_outfunction crystalcove_gpio_getfunction crystalcove_gpio_setfunction crystalcove_irq_typefunction crystalcove_bus_lockfunction crystalcove_bus_sync_unlockfunction crystalcove_irq_unmaskfunction crystalcove_irq_maskfunction crystalcove_gpio_irq_handlerfunction for_each_set_bitfunction crystalcove_gpio_dbg_showfunction crystalcove_gpio_probe
Annotated Snippet
struct crystalcove_gpio {
struct mutex buslock; /* irq_bus_lock */
struct gpio_chip chip;
struct regmap *regmap;
int update;
int intcnt_value;
bool set_irq_mask;
};
static inline int to_reg(int gpio, enum ctrl_register reg_type)
{
int reg;
if (gpio >= CRYSTALCOVE_GPIO_NUM) {
/*
* Virtual GPIO called from ACPI, for now we only support
* the panel ctl.
*/
switch (gpio) {
case 0x5e:
return GPIOPANELCTL;
default:
return -ENOTSUPP;
}
}
if (reg_type == CTRL_IN) {
if (gpio < 8)
reg = GPIO0P0CTLI;
else
reg = GPIO1P0CTLI;
} else {
if (gpio < 8)
reg = GPIO0P0CTLO;
else
reg = GPIO1P0CTLO;
}
return reg + gpio % 8;
}
static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg, int gpio)
{
u8 mirqs0 = gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0;
int mask = BIT(gpio % 8);
if (cg->set_irq_mask)
regmap_update_bits(cg->regmap, mirqs0, mask, mask);
else
regmap_update_bits(cg->regmap, mirqs0, mask, 0);
}
static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)
{
int reg = to_reg(gpio, CTRL_IN);
regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);
}
static int crystalcove_gpio_dir_in(struct gpio_chip *chip, unsigned int gpio)
{
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
int reg = to_reg(gpio, CTRL_OUT);
if (reg < 0)
return 0;
return regmap_write(cg->regmap, reg, CTLO_INPUT_SET);
}
static int crystalcove_gpio_dir_out(struct gpio_chip *chip, unsigned int gpio, int value)
{
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
int reg = to_reg(gpio, CTRL_OUT);
if (reg < 0)
return 0;
return regmap_write(cg->regmap, reg, CTLO_OUTPUT_SET | value);
}
static int crystalcove_gpio_get(struct gpio_chip *chip, unsigned int gpio)
{
struct crystalcove_gpio *cg = gpiochip_get_data(chip);
unsigned int val;
int ret, reg = to_reg(gpio, CTRL_IN);
if (reg < 0)
return 0;
Annotation
- Immediate include surface: `linux/bitops.h`, `linux/gpio/driver.h`, `linux/interrupt.h`, `linux/mfd/intel_soc_pmic.h`, `linux/module.h`, `linux/platform_device.h`, `linux/regmap.h`, `linux/seq_file.h`.
- Detected declarations: `struct crystalcove_gpio`, `enum ctrl_register`, `function to_reg`, `function crystalcove_update_irq_mask`, `function crystalcove_update_irq_ctrl`, `function crystalcove_gpio_dir_in`, `function crystalcove_gpio_dir_out`, `function crystalcove_gpio_get`, `function crystalcove_gpio_set`, `function crystalcove_irq_type`.
- Atlas domain: Driver Families / drivers/gpio.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.