drivers/gpio/gpio-gw-pld.c
Source file repositories/reference/linux-study-clean/drivers/gpio/gpio-gw-pld.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpio/gpio-gw-pld.c- Extension
.c- Size
- 3197 bytes
- Lines
- 136
- Domain
- Driver Families
- Bucket
- drivers/gpio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/bits.hlinux/kernel.hlinux/slab.hlinux/gpio/driver.hlinux/i2c.hlinux/module.h
Detected Declarations
struct gw_pldfunction gw_pld_input8function gw_pld_get8function gw_pld_output8function gw_pld_set8function gw_pld_probe
Annotated Snippet
struct gw_pld {
struct gpio_chip chip;
struct i2c_client *client;
u8 out;
};
/*
* The Gateworks I2C PLD chip only expose one read and one write register.
* Writing a "one" bit (to match the reset state) lets that pin be used as an
* input. It is an open-drain model.
*/
static int gw_pld_input8(struct gpio_chip *gc, unsigned offset)
{
struct gw_pld *gw = gpiochip_get_data(gc);
gw->out |= BIT(offset);
return i2c_smbus_write_byte(gw->client, gw->out);
}
static int gw_pld_get8(struct gpio_chip *gc, unsigned offset)
{
struct gw_pld *gw = gpiochip_get_data(gc);
s32 val;
val = i2c_smbus_read_byte(gw->client);
return (val < 0) ? 0 : !!(val & BIT(offset));
}
static int gw_pld_output8(struct gpio_chip *gc, unsigned offset, int value)
{
struct gw_pld *gw = gpiochip_get_data(gc);
if (value)
gw->out |= BIT(offset);
else
gw->out &= ~BIT(offset);
return i2c_smbus_write_byte(gw->client, gw->out);
}
static int gw_pld_set8(struct gpio_chip *gc, unsigned int offset, int value)
{
return gw_pld_output8(gc, offset, value);
}
static int gw_pld_probe(struct i2c_client *client)
{
struct device *dev = &client->dev;
struct gw_pld *gw;
int ret;
gw = devm_kzalloc(dev, sizeof(*gw), GFP_KERNEL);
if (!gw)
return -ENOMEM;
gw->chip.base = -1;
gw->chip.can_sleep = true;
gw->chip.parent = dev;
gw->chip.owner = THIS_MODULE;
gw->chip.label = dev_name(dev);
gw->chip.ngpio = 8;
gw->chip.direction_input = gw_pld_input8;
gw->chip.get = gw_pld_get8;
gw->chip.direction_output = gw_pld_output8;
gw->chip.set = gw_pld_set8;
gw->client = client;
/*
* The Gateworks I2C PLD chip does not properly send the acknowledge
* bit at all times, but we can still use the standard i2c_smbus
* functions by simply ignoring this bit.
*/
client->flags |= I2C_M_IGNORE_NAK;
gw->out = 0xFF;
i2c_set_clientdata(client, gw);
ret = devm_gpiochip_add_data(dev, &gw->chip, gw);
if (ret)
return ret;
dev_info(dev, "registered Gateworks PLD GPIO device\n");
return 0;
}
static const struct i2c_device_id gw_pld_id[] = {
{ .name = "gw-pld" },
{ }
Annotation
- Immediate include surface: `linux/bits.h`, `linux/kernel.h`, `linux/slab.h`, `linux/gpio/driver.h`, `linux/i2c.h`, `linux/module.h`.
- Detected declarations: `struct gw_pld`, `function gw_pld_input8`, `function gw_pld_get8`, `function gw_pld_output8`, `function gw_pld_set8`, `function gw_pld_probe`.
- Atlas domain: Driver Families / drivers/gpio.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.