drivers/gpio/gpio-omap.c
Source file repositories/reference/linux-study-clean/drivers/gpio/gpio-omap.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpio/gpio-omap.c- Extension
.c- Size
- 43540 bytes
- Lines
- 1605
- Domain
- Driver Families
- Bucket
- drivers/gpio
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/init.hlinux/module.hlinux/interrupt.hlinux/seq_file.hlinux/syscore_ops.hlinux/err.hlinux/clk.hlinux/io.hlinux/cpu_pm.hlinux/device.hlinux/pm_runtime.hlinux/pm.hlinux/of.hlinux/gpio/driver.hlinux/bitops.hlinux/platform_data/gpio-omap.h
Detected Declarations
struct gpio_regsstruct gpio_bankfunction omap_gpio_rmwfunction omap_set_gpio_directionfunction omap_set_gpio_dataout_regfunction omap_set_gpio_dataout_maskfunction omap_gpio_dbck_enablefunction omap_gpio_dbck_disablefunction omap2_set_gpio_debouncefunction omap_clear_gpio_debouncefunction omap_gpio_is_off_wakeup_capablefunction omap_set_gpio_triggerfunction omap_toggle_gpio_edge_triggeringfunction omap_set_gpio_triggeringfunction omap_enable_gpio_modulefunction omap_disable_gpio_modulefunction omap_gpio_is_inputfunction omap_gpio_init_irqfunction omap_gpio_irq_typefunction omap_clear_gpio_irqbankfunction omap_clear_gpio_irqstatusfunction omap_get_gpio_irqbank_maskfunction omap_set_gpio_irqenablefunction omap_gpio_wake_enablefunction omap_gpio_irq_handlerfunction omap_gpio_irq_startupfunction omap_gpio_irq_shutdownfunction omap_gpio_irq_bus_lockfunction gpio_irq_bus_sync_unlockfunction omap_gpio_mask_irqfunction omap_gpio_unmask_irqfunction omap_gpio_irq_print_chipfunction omap_mpuio_suspend_noirqfunction omap_mpuio_resume_noirqfunction omap_mpuio_initfunction omap_gpio_requestfunction omap_gpio_freefunction omap_gpio_get_directionfunction omap_gpio_inputfunction omap_gpio_getfunction omap_gpio_outputfunction omap_gpio_get_multiplefunction omap_gpio_debouncefunction omap_gpio_set_configfunction omap_gpio_setfunction omap_gpio_set_multiplefunction omap_gpio_show_revfunction omap_gpio_mod_init
Annotated Snippet
struct gpio_regs {
u32 sysconfig;
u32 irqenable1;
u32 irqenable2;
u32 wake_en;
u32 ctrl;
u32 oe;
u32 leveldetect0;
u32 leveldetect1;
u32 risingdetect;
u32 fallingdetect;
u32 dataout;
u32 debounce;
u32 debounce_en;
};
struct gpio_bank {
void __iomem *base;
const struct omap_gpio_reg_offs *regs;
struct device *dev;
int irq;
u32 non_wakeup_gpios;
u32 enabled_non_wakeup_gpios;
struct gpio_regs context;
u32 saved_datain;
u32 level_mask;
u32 toggle_mask;
raw_spinlock_t lock;
raw_spinlock_t wa_lock;
struct gpio_chip chip;
struct clk *dbck;
struct notifier_block nb;
unsigned int is_suspended:1;
unsigned int needs_resume:1;
u32 mod_usage;
u32 irq_usage;
u32 dbck_enable_mask;
bool dbck_enabled;
bool is_mpuio;
bool dbck_flag;
bool loses_context;
bool context_valid;
int stride;
u32 width;
int context_loss_count;
void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
int (*get_context_loss_count)(struct device *dev);
};
#define GPIO_MOD_CTRL_BIT BIT(0)
#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
#define LINE_USED(line, offset) (line & (BIT(offset)))
static void omap_gpio_unmask_irq(struct irq_data *d);
static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
{
struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
return gpiochip_get_data(chip);
}
static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
{
u32 val = readl_relaxed(reg);
if (set)
val |= mask;
else
val &= ~mask;
writel_relaxed(val, reg);
return val;
}
static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
int is_input)
{
bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
BIT(gpio), is_input);
}
/* set data out value using dedicate set/clear register */
static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
int enable)
{
Annotation
- Immediate include surface: `linux/init.h`, `linux/module.h`, `linux/interrupt.h`, `linux/seq_file.h`, `linux/syscore_ops.h`, `linux/err.h`, `linux/clk.h`, `linux/io.h`.
- Detected declarations: `struct gpio_regs`, `struct gpio_bank`, `function omap_gpio_rmw`, `function omap_set_gpio_direction`, `function omap_set_gpio_dataout_reg`, `function omap_set_gpio_dataout_mask`, `function omap_gpio_dbck_enable`, `function omap_gpio_dbck_disable`, `function omap2_set_gpio_debounce`, `function omap_clear_gpio_debounce`.
- Atlas domain: Driver Families / drivers/gpio.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.