drivers/gpio/gpio-qixis-fpga.c
Source file repositories/reference/linux-study-clean/drivers/gpio/gpio-qixis-fpga.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpio/gpio-qixis-fpga.c- Extension
.c- Size
- 2738 bytes
- Lines
- 112
- Domain
- Driver Families
- Bucket
- drivers/gpio
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/device.hlinux/gpio/driver.hlinux/gpio/regmap.hlinux/kernel.hlinux/mod_devicetable.hlinux/module.hlinux/platform_device.hlinux/regmap.h
Detected Declarations
struct qixis_cpld_gpio_configfunction qixis_cpld_gpio_probe
Annotated Snippet
struct qixis_cpld_gpio_config {
u64 output_lines;
};
static const struct qixis_cpld_gpio_config lx2160ardb_sfp_cfg = {
.output_lines = BIT(0),
};
static const struct qixis_cpld_gpio_config ls1046aqds_stat_pres2_cfg = {
.output_lines = 0x0,
};
static const struct regmap_config regmap_config_8r_8v = {
.reg_bits = 8,
.val_bits = 8,
};
static int qixis_cpld_gpio_probe(struct platform_device *pdev)
{
DECLARE_BITMAP(fixed_direction_output, 8);
const struct qixis_cpld_gpio_config *cfg;
struct gpio_regmap_config config = {0};
struct regmap *regmap;
void __iomem *reg;
u32 base;
int ret;
if (!pdev->dev.parent)
return -ENODEV;
cfg = device_get_match_data(&pdev->dev);
ret = device_property_read_u32(&pdev->dev, "reg", &base);
if (ret)
return ret;
regmap = dev_get_regmap(pdev->dev.parent, NULL);
if (!regmap) {
/* In case there is no regmap configured by the parent device,
* create our own from the MMIO space.
*/
reg = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(reg))
return PTR_ERR(reg);
regmap = devm_regmap_init_mmio(&pdev->dev, reg, ®map_config_8r_8v);
if (IS_ERR(regmap))
return PTR_ERR(regmap);
/* In this case, the offset of our register is 0 inside the
* regmap area that we just created.
*/
base = 0;
}
config.reg_dat_base = GPIO_REGMAP_ADDR(base);
config.reg_set_base = GPIO_REGMAP_ADDR(base);
config.drvdata = (void *)cfg;
config.regmap = regmap;
config.parent = &pdev->dev;
config.ngpio_per_reg = 8;
config.ngpio = 8;
bitmap_from_u64(fixed_direction_output, cfg->output_lines);
config.fixed_direction_output = fixed_direction_output;
return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config));
}
static const struct of_device_id qixis_cpld_gpio_of_match[] = {
{
.compatible = "fsl,lx2160ardb-fpga-gpio-sfp",
.data = &lx2160ardb_sfp_cfg,
},
{
.compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2",
.data = &ls1046aqds_stat_pres2_cfg,
},
{}
};
MODULE_DEVICE_TABLE(of, qixis_cpld_gpio_of_match);
static struct platform_driver qixis_cpld_gpio_driver = {
.probe = qixis_cpld_gpio_probe,
.driver = {
.name = "gpio-qixis-cpld",
.of_match_table = qixis_cpld_gpio_of_match,
},
};
Annotation
- Immediate include surface: `linux/device.h`, `linux/gpio/driver.h`, `linux/gpio/regmap.h`, `linux/kernel.h`, `linux/mod_devicetable.h`, `linux/module.h`, `linux/platform_device.h`, `linux/regmap.h`.
- Detected declarations: `struct qixis_cpld_gpio_config`, `function qixis_cpld_gpio_probe`.
- Atlas domain: Driver Families / drivers/gpio.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.