drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c- Extension
.c- Size
- 25627 bytes
- Lines
- 1022
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
drm/drm_auth.hdrm/drm_drv.hamdgpu.hamdgpu_sched.hamdgpu_ras.hlinux/nospec.h
Detected Declarations
function amdgpu_ctx_priority_is_validfunction amdgpu_ctx_to_drm_sched_priofunction amdgpu_ctx_priority_permitfunction amdgpu_ctx_prio_to_gfx_pipe_priofunction amdgpu_ctx_sched_prio_to_ring_priofunction amdgpu_ctx_get_hw_priofunction amdgpu_ctx_fence_timefunction amdgpu_ctx_entity_timefunction amdgpu_ctx_init_entityfunction amdgpu_ctx_fini_entityfunction amdgpu_ctx_get_stable_pstatefunction amdgpu_ctx_initfunction amdgpu_ctx_set_stable_pstatefunction amdgpu_ctx_finifunction amdgpu_ctx_get_entityfunction amdgpu_ctx_allocfunction amdgpu_ctx_do_releasefunction amdgpu_ctx_freefunction amdgpu_ctx_queryfunction amdgpu_ctx_guiltyfunction amdgpu_ctx_query2function amdgpu_ctx_stable_pstatefunction amdgpu_ctx_ioctlfunction amdgpu_ctx_putfunction amdgpu_ctx_add_fencefunction amdgpu_ctx_set_entity_priorityfunction amdgpu_ctx_priority_overridefunction amdgpu_ctx_wait_prev_fencefunction amdgpu_ctx_mgr_initfunction amdgpu_ctx_mgr_entity_flushfunction amdgpu_ctx_mgr_entity_finifunction idr_for_each_entryfunction amdgpu_ctx_mgr_finifunction amdgpu_ctx_mgr_usagefunction idr_for_each_entry
Annotated Snippet
if (ce_count != ctx->ras_counter_ce) {
ctx->ras_counter_ce = ce_count;
out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_CE;
}
if (ue_count != ctx->ras_counter_ue) {
ctx->ras_counter_ue = ue_count;
out->state.flags |= AMDGPU_CTX_QUERY2_FLAGS_RAS_UE;
}
schedule_delayed_work(&con->ras_counte_delay_work,
msecs_to_jiffies(AMDGPU_RAS_COUNTE_DELAY_MS));
}
mutex_unlock(&mgr->lock);
return 0;
}
static int amdgpu_ctx_stable_pstate(struct amdgpu_device *adev,
struct amdgpu_fpriv *fpriv, uint32_t id,
bool set, u32 *stable_pstate)
{
struct amdgpu_ctx *ctx;
struct amdgpu_ctx_mgr *mgr;
int r;
if (!fpriv)
return -EINVAL;
mgr = &fpriv->ctx_mgr;
mutex_lock(&mgr->lock);
ctx = idr_find(&mgr->ctx_handles, id);
if (!ctx) {
mutex_unlock(&mgr->lock);
return -EINVAL;
}
if (set)
r = amdgpu_ctx_set_stable_pstate(ctx, *stable_pstate);
else
r = amdgpu_ctx_get_stable_pstate(ctx, stable_pstate);
mutex_unlock(&mgr->lock);
return r;
}
int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
struct drm_file *filp)
{
int r;
uint32_t id, stable_pstate;
int32_t priority;
union drm_amdgpu_ctx *args = data;
struct amdgpu_device *adev = drm_to_adev(dev);
struct amdgpu_fpriv *fpriv = filp->driver_priv;
id = args->in.ctx_id;
priority = args->in.priority;
/* For backwards compatibility, we need to accept ioctls with garbage
* in the priority field. Garbage values in the priority field, result
* in the priority being set to NORMAL.
*/
if (!amdgpu_ctx_priority_is_valid(priority))
priority = AMDGPU_CTX_PRIORITY_NORMAL;
switch (args->in.op) {
case AMDGPU_CTX_OP_ALLOC_CTX:
if (args->in.flags)
return -EINVAL;
r = amdgpu_ctx_alloc(adev, fpriv, filp, priority, &id);
args->out.alloc.ctx_id = id;
break;
case AMDGPU_CTX_OP_FREE_CTX:
if (args->in.flags)
return -EINVAL;
r = amdgpu_ctx_free(fpriv, id);
break;
case AMDGPU_CTX_OP_QUERY_STATE:
if (args->in.flags)
return -EINVAL;
r = amdgpu_ctx_query(adev, fpriv, id, &args->out);
break;
case AMDGPU_CTX_OP_QUERY_STATE2:
if (args->in.flags)
return -EINVAL;
r = amdgpu_ctx_query2(adev, fpriv, id, &args->out);
break;
case AMDGPU_CTX_OP_GET_STABLE_PSTATE:
Annotation
- Immediate include surface: `drm/drm_auth.h`, `drm/drm_drv.h`, `amdgpu.h`, `amdgpu_sched.h`, `amdgpu_ras.h`, `linux/nospec.h`.
- Detected declarations: `function amdgpu_ctx_priority_is_valid`, `function amdgpu_ctx_to_drm_sched_prio`, `function amdgpu_ctx_priority_permit`, `function amdgpu_ctx_prio_to_gfx_pipe_prio`, `function amdgpu_ctx_sched_prio_to_ring_prio`, `function amdgpu_ctx_get_hw_prio`, `function amdgpu_ctx_fence_time`, `function amdgpu_ctx_entity_time`, `function amdgpu_ctx_init_entity`, `function amdgpu_ctx_fini_entity`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.