drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c- Extension
.c- Size
- 102225 bytes
- Lines
- 3487
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/firmware.hamdgpu.hamdgpu_discovery.hsoc15_hw_ip.hdiscovery.hamdgpu_ras.hsoc15.hgfx_v9_0.hgfx_v9_4_3.hgmc_v9_0.hdf_v1_7.hdf_v3_6.hdf_v4_3.hdf_v4_6_2.hdf_v4_15.hnbio_v6_1.hnbio_v7_0.hnbio_v7_4.hnbio_v7_9.hnbio_v7_11.hhdp_v4_0.hvega10_ih.hvega20_ih.hsdma_v4_0.hsdma_v4_4_2.huvd_v7_0.hvce_v4_0.hvcn_v1_0.hvcn_v2_5.hjpeg_v2_5.hsmuio_v9_0.hgmc_v10_0.h
Detected Declarations
struct ip_hw_instancestruct ip_hw_idstruct ip_die_entrystruct ip_hw_instance_attrstruct ip_die_entry_attributestruct ip_discovery_topfunction amdgpu_discovery_get_tmr_infofunction amdgpu_discovery_read_binary_from_sysmemfunction amdgpu_discovery_read_binary_from_memfunction amdgpu_discovery_read_binary_from_filefunction amdgpu_discovery_calculate_checksumfunction amdgpu_discovery_verify_checksumfunction amdgpu_discovery_verify_binary_signaturefunction amdgpu_discovery_harvest_config_quirkfunction amdgpu_discovery_verify_npsinfofunction amdgpu_discovery_get_table_infofunction amdgpu_discovery_table_checkfunction amdgpu_discovery_initfunction amdgpu_discovery_finifunction amdgpu_discovery_validate_ipfunction amdgpu_discovery_read_harvest_bit_per_ipfunction amdgpu_discovery_read_from_harvest_tablefunction hw_id_showfunction num_instance_showfunction major_showfunction minor_showfunction revision_showfunction harvest_showfunction num_base_addresses_showfunction base_addr_showfunction ip_hw_instance_attr_showfunction ip_hw_instance_releasefunction ip_hw_id_releasefunction num_ips_showfunction ip_die_entry_attr_showfunction ip_die_entry_releasefunction die_kobj_releasefunction ip_disc_releasefunction amdgpu_discovery_get_harvest_infofunction amdgpu_discovery_sysfs_ipsfunction amdgpu_discovery_sysfs_recursefunction amdgpu_discovery_sysfs_initfunction amdgpu_discovery_sysfs_ip_hw_freefunction amdgpu_discovery_sysfs_die_freefunction amdgpu_discovery_sysfs_finifunction amdgpu_discovery_dumpfunction list_for_eachfunction list_for_each
Annotated Snippet
struct ip_hw_instance {
struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */
int hw_id;
u8 num_instance;
u8 major, minor, revision;
u8 harvest;
int num_base_addresses;
u32 base_addr[] __counted_by(num_base_addresses);
};
struct ip_hw_id {
struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */
int hw_id;
};
struct ip_die_entry {
struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */
u16 num_ips;
};
/* -------------------------------------------------- */
struct ip_hw_instance_attr {
struct attribute attr;
ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf);
};
static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf)
{
return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id);
}
static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf)
{
return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance);
}
static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf)
{
return sysfs_emit(buf, "%d\n", ip_hw_instance->major);
}
static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf)
{
return sysfs_emit(buf, "%d\n", ip_hw_instance->minor);
}
static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf)
{
return sysfs_emit(buf, "%d\n", ip_hw_instance->revision);
}
static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf)
{
return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest);
}
static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf)
{
return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses);
}
static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf)
{
ssize_t at;
int ii;
for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) {
/* Here we satisfy the condition that, at + size <= PAGE_SIZE.
*/
if (at + 12 > PAGE_SIZE)
break;
at += sysfs_emit_at(buf, at, "0x%08X\n",
ip_hw_instance->base_addr[ii]);
}
return at;
}
static struct ip_hw_instance_attr ip_hw_attr[] = {
__ATTR_RO(hw_id),
__ATTR_RO(num_instance),
__ATTR_RO(major),
__ATTR_RO(minor),
__ATTR_RO(revision),
__ATTR_RO(harvest),
__ATTR_RO(num_base_addresses),
__ATTR_RO(base_addr),
Annotation
- Immediate include surface: `linux/firmware.h`, `amdgpu.h`, `amdgpu_discovery.h`, `soc15_hw_ip.h`, `discovery.h`, `amdgpu_ras.h`, `soc15.h`, `gfx_v9_0.h`.
- Detected declarations: `struct ip_hw_instance`, `struct ip_hw_id`, `struct ip_die_entry`, `struct ip_hw_instance_attr`, `struct ip_die_entry_attribute`, `struct ip_discovery_top`, `function amdgpu_discovery_get_tmr_info`, `function amdgpu_discovery_read_binary_from_sysmem`, `function amdgpu_discovery_read_binary_from_mem`, `function amdgpu_discovery_read_binary_from_file`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.