drivers/gpu/drm/amd/amdgpu/amdgpu.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu.h- Extension
.h- Size
- 51447 bytes
- Lines
- 1637
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu_ctx.hlinux/atomic.hlinux/wait.hlinux/list.hlinux/kref.hlinux/rbtree.hlinux/hashtable.hlinux/dma-fence.hlinux/pci.hdrm/ttm/ttm_bo.hdrm/ttm/ttm_placement.hdrm/amdgpu_drm.hdrm/drm_gem.hdrm/drm_ioctl.hkgd_kfd_interface.hdm_pp_interface.hkgd_pp_interface.hamd_shared.hamdgpu_utils.hamdgpu_mode.hamdgpu_ih.hamdgpu_irq.hamdgpu_ucode.hamdgpu_ttm.hamdgpu_psp.hamdgpu_gds.hamdgpu_sync.hamdgpu_ring.hamdgpu_vm.hamdgpu_dpm.hamdgpu_acp.hamdgpu_uvd.h
Detected Declarations
struct amdgpu_gpu_instancestruct amdgpu_mgpu_infostruct amdgpu_hwip_reg_entrystruct amdgpu_watchdog_timerstruct amdgpu_xcp_mgrstruct amdgpu_devicestruct amdgpu_irq_srcstruct amdgpu_fprivstruct amdgpu_bo_va_mappingstruct kfd_vm_fault_infostruct amdgpu_hive_infostruct amdgpu_reset_contextstruct amdgpu_reset_controlstruct amdgpu_coredump_infostruct amdgpu_clockstruct amdgpu_sa_managerstruct amdgpu_flip_workstruct amdgpu_fprivstruct amdgpu_wbstruct amdgpu_allowed_register_entrystruct amdgpu_video_codec_infostruct amdgpu_video_codecsstruct amdgpu_asic_funcsstruct amdgpu_mem_scratchstruct amdgpu_mmio_remapstruct amdgpu_uidstruct amdgpu_uma_carveout_optionstruct amdgpu_uma_carveout_infostruct amd_powerplaystruct amdgpu_mqd_propstruct amdgpu_mqdstruct amdgpu_pcie_reset_ctxstruct amdgpu_init_levelstruct amdgpu_reset_domainstruct amdgpu_fru_infostruct amdgpu_devicestruct amdgpu_isolationstruct amdgpu_afmt_acrstruct amdgpu_numa_infoenum amdgpu_ssenum amdgpu_cp_irqenum amdgpu_thermal_irqenum amdgpu_kiq_irqenum amdgpu_uid_typeenum amdgpu_mqd_update_flagenum amdgpu_init_lvl_idenum amdgpu_enforce_isolation_modefunction address
Annotated Snippet
struct amdgpu_gpu_instance {
struct amdgpu_device *adev;
int mgpu_fan_enabled;
};
struct amdgpu_mgpu_info {
struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE];
struct mutex mutex;
uint32_t num_gpu;
uint32_t num_dgpu;
uint32_t num_apu;
};
enum amdgpu_ss {
AMDGPU_SS_DRV_LOAD,
AMDGPU_SS_DEV_D0,
AMDGPU_SS_DEV_D3,
AMDGPU_SS_DRV_UNLOAD
};
struct amdgpu_hwip_reg_entry {
u32 hwip;
u32 inst;
u32 seg;
u32 reg_offset;
const char *reg_name;
};
struct amdgpu_watchdog_timer {
bool timeout_fatal_disable;
uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */
};
#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
/*
* Modules parameters.
*/
extern int amdgpu_modeset;
extern unsigned int amdgpu_vram_limit;
extern int amdgpu_vis_vram_limit;
extern int amdgpu_gart_size;
extern int amdgpu_gtt_size;
extern int amdgpu_moverate;
extern int amdgpu_audio;
extern int amdgpu_disp_priority;
extern int amdgpu_hw_i2c;
extern int amdgpu_pcie_gen2;
extern int amdgpu_msi;
extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
extern int amdgpu_dpm;
extern int amdgpu_fw_load_type;
extern int amdgpu_aspm;
extern int amdgpu_runtime_pm;
extern uint amdgpu_ip_block_mask;
extern int amdgpu_bapm;
extern int amdgpu_deep_color;
extern int amdgpu_vm_size;
extern int amdgpu_vm_block_size;
extern int amdgpu_vm_fragment_size;
extern int amdgpu_vm_fault_stop;
extern int amdgpu_vm_debug;
extern int amdgpu_vm_update_mode;
extern int amdgpu_exp_hw_support;
extern int amdgpu_dc;
extern int amdgpu_sched_jobs;
extern int amdgpu_sched_hw_submission;
extern uint amdgpu_pcie_gen_cap;
extern uint amdgpu_pcie_lane_cap;
extern u64 amdgpu_cg_mask;
extern uint amdgpu_pg_mask;
extern uint amdgpu_sdma_phase_quantum;
extern char *amdgpu_disable_cu;
extern char *amdgpu_virtual_display;
extern uint amdgpu_pp_feature_mask;
extern uint amdgpu_force_long_training;
extern int amdgpu_lbpw;
extern int amdgpu_compute_multipipe;
extern int amdgpu_gpu_recovery;
extern int amdgpu_emu_mode;
extern uint amdgpu_smu_memory_pool_size;
extern int amdgpu_smu_pptable_id;
extern uint amdgpu_dc_feature_mask;
extern uint amdgpu_freesync_vid_mode;
extern uint amdgpu_dc_debug_mask;
extern uint amdgpu_dc_visual_confirm;
extern int amdgpu_dm_abm_level;
extern int amdgpu_backlight;
extern int amdgpu_damage_clips;
extern struct amdgpu_mgpu_info mgpu_info;
Annotation
- Immediate include surface: `amdgpu_ctx.h`, `linux/atomic.h`, `linux/wait.h`, `linux/list.h`, `linux/kref.h`, `linux/rbtree.h`, `linux/hashtable.h`, `linux/dma-fence.h`.
- Detected declarations: `struct amdgpu_gpu_instance`, `struct amdgpu_mgpu_info`, `struct amdgpu_hwip_reg_entry`, `struct amdgpu_watchdog_timer`, `struct amdgpu_xcp_mgr`, `struct amdgpu_device`, `struct amdgpu_irq_src`, `struct amdgpu_fpriv`, `struct amdgpu_bo_va_mapping`, `struct kfd_vm_fault_info`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.