drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c- Extension
.c- Size
- 8937 bytes
- Lines
- 318
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dma-mapping.hamdgpu.hamdgpu_ih.hamdgpu_reset.h
Detected Declarations
function filesfunction amdgpu_ih_ring_finifunction amdgpu_ih_ring_writefunction amdgpu_ih_wait_on_checkpoint_process_tsfunction handerfunction amdgpu_ih_decode_iv_helperfunction amdgpu_ih_decode_iv_ts_helper
Annotated Snippet
if (r) {
amdgpu_device_wb_free(adev, wptr_offs);
return r;
}
r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE,
AMDGPU_GEM_DOMAIN_GTT,
&ih->ring_obj, &ih->gpu_addr,
(void **)&ih->ring);
if (r) {
amdgpu_device_wb_free(adev, rptr_offs);
amdgpu_device_wb_free(adev, wptr_offs);
return r;
}
ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
ih->wptr_cpu = &adev->wb.wb[wptr_offs];
ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
ih->rptr_cpu = &adev->wb.wb[rptr_offs];
}
init_waitqueue_head(&ih->wait_process);
return 0;
}
/**
* amdgpu_ih_ring_fini - tear down the IH state
*
* @adev: amdgpu_device pointer
* @ih: ih ring to tear down
*
* Tears down the IH state and frees buffer
* used for the IH ring buffer.
*/
void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
{
if (!ih->ring)
return;
if (ih->use_bus_addr) {
/* add 8 bytes for the rptr/wptr shadows and
* add them to the end of the ring allocation.
*/
dma_free_coherent(adev->dev, ih->ring_size + 8,
(void *)ih->ring, ih->gpu_addr);
ih->ring = NULL;
} else {
amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
(void **)&ih->ring);
amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
}
}
/**
* amdgpu_ih_ring_write - write IV to the ring buffer
*
* @adev: amdgpu_device pointer
* @ih: ih ring to write to
* @iv: the iv to write
* @num_dw: size of the iv in dw
*
* Writes an IV to the ring buffer using the CPU and increment the wptr.
* Used for testing and delegating IVs to a software ring.
*/
void amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
const uint32_t *iv, unsigned int num_dw)
{
uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2;
unsigned int i;
for (i = 0; i < num_dw; ++i)
ih->ring[wptr++] = cpu_to_le32(iv[i]);
wptr <<= 2;
wptr &= ih->ptr_mask;
/* Only commit the new wptr if we don't overflow */
if (wptr != READ_ONCE(ih->rptr)) {
wmb();
WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr));
} else if (adev->irq.retry_cam_enabled) {
dev_warn_once(adev->dev, "IH soft ring buffer overflow 0x%X, 0x%X\n",
wptr, ih->rptr);
}
}
/**
Annotation
- Immediate include surface: `linux/dma-mapping.h`, `amdgpu.h`, `amdgpu_ih.h`, `amdgpu_reset.h`.
- Detected declarations: `function files`, `function amdgpu_ih_ring_fini`, `function amdgpu_ih_ring_write`, `function amdgpu_ih_wait_on_checkpoint_process_ts`, `function hander`, `function amdgpu_ih_decode_iv_helper`, `function amdgpu_ih_decode_iv_ts_helper`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.