drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
Extension
.c
Size
26169 bytes
Lines
884
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (r) {
			dev_err(adev->dev,
				"(%d) ring trail_fence_offs wb alloc failed\n",
				r);
			goto error;
		}
		adev->mes.sch_ctx_gpu_addr[i] =
			adev->wb.gpu_addr + (adev->mes.sch_ctx_offs[i] * 4);
		adev->mes.sch_ctx_ptr[i] =
			(uint64_t *)&adev->wb.wb[adev->mes.sch_ctx_offs[i]];

		r = amdgpu_device_wb_get(adev,
				 &adev->mes.query_status_fence_offs[i]);
		if (r) {
			dev_err(adev->dev,
			      "(%d) query_status_fence_offs wb alloc failed\n",
			      r);
			goto error;
		}
		adev->mes.query_status_fence_gpu_addr[i] = adev->wb.gpu_addr +
			(adev->mes.query_status_fence_offs[i] * 4);
		adev->mes.query_status_fence_ptr[i] =
			(uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs[i]];
	}

	r = amdgpu_mes_doorbell_init(adev);
	if (r)
		goto error;

	r = amdgpu_mes_event_log_init(adev);
	if (r)
		goto error_doorbell;

	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0)) {
		/* When queue/pipe reset is done in MES instead of in the
		 * driver, MES passes hung queues information to the driver in
		 * hung_queue_hqd_info. Calculate required space to store this
		 * information.
		 */
		for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++)
			num_queues += hweight32(adev->mes.gfx_hqd_mask[i]);

		for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++)
			num_queues += hweight32(adev->mes.compute_hqd_mask[i]);

		for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++)
			num_queues += hweight32(adev->mes.sdma_hqd_mask[i]) * num_xcc;

		adev->mes.hung_queue_hqd_info_offset = num_queues;
		adev->mes.hung_queue_db_array_size = num_queues * 2;
	}

	if (adev->mes.hung_queue_db_array_size) {
		for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
			r = amdgpu_bo_create_kernel(adev,
						    adev->mes.hung_queue_db_array_size * sizeof(u32),
						    PAGE_SIZE,
						    AMDGPU_GEM_DOMAIN_GTT,
						    &adev->mes.hung_queue_db_array_gpu_obj[i],
						    &adev->mes.hung_queue_db_array_gpu_addr[i],
						    &adev->mes.hung_queue_db_array_cpu_addr[i]);
			if (r) {
				dev_warn(adev->dev, "failed to create MES hung db array buffer (%d)", r);
				goto error_doorbell;
			}
		}
	}

	return 0;

error_doorbell:
	amdgpu_mes_doorbell_free(adev);
error:
	for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) {
		if (adev->mes.sch_ctx_ptr[i])
			amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]);
		if (adev->mes.query_status_fence_ptr[i])
			amdgpu_device_wb_free(adev,
				      adev->mes.query_status_fence_offs[i]);
		if (adev->mes.hung_queue_db_array_gpu_obj[i])
			amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i],
					      &adev->mes.hung_queue_db_array_gpu_addr[i],
					      &adev->mes.hung_queue_db_array_cpu_addr[i]);
	}

	ida_destroy(&adev->mes.doorbell_ida);
	mutex_destroy(&adev->mes.mutex_hidden);
	return r;
}

Annotation

Implementation Notes