drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_mes_ctx.h
Extension
.h
Size
3486 bytes
Lines
123
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct amdgpu_wb_slot {
	uint32_t data[8];
};

struct amdgpu_mes_ctx_meta_data {
	struct {
		uint8_t ring[PAGE_SIZE * 4];

		/* gfx csa */
		struct v10_gfx_meta_data gfx_meta_data;

		uint8_t gds_backup[64 * 1024];

		struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];

		/* only for ib test */
		uint32_t ib[256] __aligned(256);

		uint32_t padding[64];

	} __aligned(PAGE_SIZE) gfx[AMDGPU_MES_CTX_MAX_GFX_RINGS];

	struct {
		uint8_t ring[PAGE_SIZE * 4];

		uint8_t mec_hpd[GFX10_MEC_HPD_SIZE];

		struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];

		/* only for ib test */
		uint32_t ib[256] __aligned(256);

		uint32_t padding[64];

	} __aligned(PAGE_SIZE) compute[AMDGPU_MES_CTX_MAX_COMPUTE_RINGS];

	struct {
		uint8_t ring[PAGE_SIZE * 4];

		/* sdma csa for mcbp */
		uint8_t sdma_meta_data[AMDGPU_CSA_SDMA_SIZE];

		struct amdgpu_wb_slot slots[AMDGPU_MES_CTX_MAX_OFFS];

		/* only for ib test */
		uint32_t ib[256] __aligned(256);

		uint32_t padding[64];

	} __aligned(PAGE_SIZE) sdma[AMDGPU_MES_CTX_MAX_SDMA_RINGS];
};

struct amdgpu_mes_ctx_data {
	struct amdgpu_bo	*meta_data_obj;
	uint64_t                meta_data_gpu_addr;
	uint64_t                meta_data_mc_addr;
	struct amdgpu_bo_va	*meta_data_va;
	void                    *meta_data_ptr;
	uint32_t                gang_ids[AMDGPU_HW_IP_DMA+1];
};

#define AMDGPU_FENCE_MES_QUEUE_FLAG     0x1000000u
#define AMDGPU_FENCE_MES_QUEUE_ID_MASK  (AMDGPU_FENCE_MES_QUEUE_FLAG - 1)

#define AMDGPU_FENCE_MES_QUEUE_FLAG     0x1000000u
#define AMDGPU_FENCE_MES_QUEUE_ID_MASK  (AMDGPU_FENCE_MES_QUEUE_FLAG - 1)

#endif

Annotation

Implementation Notes