drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

File Facts

System: Linux kernel
Corpus path: drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
Extension: .h
Size: 18273 bytes
Lines: 558
Domain: Driver Families
Bucket: drivers/gpu
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

amdgpu_irq.h
kgd_kfd_interface.h
amdgpu_gfx.h
amdgpu_doorbell.h
linux/sched/mm.h

Detected Declarations

struct amdgpu_mes_funcs
struct amdgpu_mes
struct amdgpu_mes_hung_queue_hqd_info
struct amdgpu_mes_gang
struct amdgpu_mes_queue
struct amdgpu_mes_queue_properties
struct amdgpu_mes_gang_properties
struct mes_add_queue_input
struct mes_remove_queue_input
struct mes_map_legacy_queue_input
struct mes_unmap_legacy_queue_input
struct mes_suspend_gang_input
struct mes_resume_gang_input
struct mes_reset_queue_input
struct mes_detect_and_reset_queue_input
struct mes_inv_tlbs_pasid_input
struct mes_misc_op_input
struct amdgpu_mes_funcs
enum amdgpu_mes_priority_level
enum amdgpu_mes_pipe
enum mes_misc_opcode
function amdgpu_mes_lock
function amdgpu_mes_unlock

Annotated Snippet

struct amdgpu_mes {
	struct amdgpu_device            *adev;

	struct mutex                    mutex_hidden;

	struct ida                      doorbell_ida;

	spinlock_t                      queue_id_lock;

	uint32_t			sched_version;
	uint32_t			kiq_version;
	uint32_t			fw_version[AMDGPU_MAX_MES_PIPES];
	bool                            enable_legacy_queue_map;

	uint32_t                        total_max_queue;
	uint32_t                        max_doorbell_slices;

	uint64_t                        default_process_quantum;
	uint64_t                        default_gang_quantum;

	struct amdgpu_ring              ring[AMDGPU_MAX_MES_INST_PIPES];
	spinlock_t                      ring_lock[AMDGPU_MAX_MES_INST_PIPES];

	const struct firmware           *fw[AMDGPU_MAX_MES_PIPES];

	/* mes ucode */
	struct amdgpu_bo		*ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES];
	uint64_t			ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
	uint32_t			*ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES];
	uint64_t                        uc_start_addr[AMDGPU_MAX_MES_PIPES];

	/* mes ucode data */
	struct amdgpu_bo		*data_fw_obj[AMDGPU_MAX_MES_INST_PIPES];
	uint64_t			data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
	uint32_t			*data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES];
	uint64_t                        data_start_addr[AMDGPU_MAX_MES_PIPES];

	/* eop gpu obj */
	struct amdgpu_bo		*eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES];
	uint64_t                        eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];

	void                            *mqd_backup[AMDGPU_MAX_MES_INST_PIPES];
	struct amdgpu_irq_src	        irq[AMDGPU_MAX_MES_INST_PIPES];

	uint32_t                        vmid_mask_gfxhub;
	uint32_t                        vmid_mask_mmhub;
	uint32_t                        gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
	uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
	uint32_t                        sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
	uint32_t                        aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];

	uint32_t                        sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES];
	uint64_t                        sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
	uint64_t                        *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES];
	uint32_t                        query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES];
	uint64_t                        query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
	uint64_t                        *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES];

	uint32_t			saved_flags;

	/* initialize kiq pipe */
	int                             (*kiq_hw_init)(struct amdgpu_device *adev,
                                                   uint32_t xcc_id);
	int                             (*kiq_hw_fini)(struct amdgpu_device *adev,
                                                   uint32_t xcc_id);

	/* MES doorbells */
	uint32_t			db_start_dw_offset;
	uint32_t			num_mes_dbs;
	unsigned long			*doorbell_bitmap;

	/* MES event log buffer */
	uint32_t			event_log_size;
	struct amdgpu_bo	*event_log_gpu_obj;
	uint64_t			event_log_gpu_addr;
	void				*event_log_cpu_addr;

	/* ip specific functions */
	const struct amdgpu_mes_funcs   *funcs;

	/* mes resource_1 bo*/
	struct amdgpu_bo    *resource_1[AMDGPU_MAX_MES_PIPES];
	uint64_t            resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES];
	void                *resource_1_addr[AMDGPU_MAX_MES_PIPES];

	int				hung_queue_db_array_size;
	int				hung_queue_hqd_info_offset;
	struct amdgpu_bo		*hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_INST_PIPES];
	uint64_t			hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
	void				*hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_INST_PIPES];

Annotation

Immediate include surface: `amdgpu_irq.h`, `kgd_kfd_interface.h`, `amdgpu_gfx.h`, `amdgpu_doorbell.h`, `linux/sched/mm.h`.
Detected declarations: `struct amdgpu_mes_funcs`, `struct amdgpu_mes`, `struct amdgpu_mes_hung_queue_hqd_info`, `struct amdgpu_mes_gang`, `struct amdgpu_mes_queue`, `struct amdgpu_mes_queue_properties`, `struct amdgpu_mes_gang_properties`, `struct mes_add_queue_input`, `struct mes_remove_queue_input`, `struct mes_map_legacy_queue_input`.
Atlas domain: Driver Families / drivers/gpu.
Implementation status: source implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.