drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c- Extension
.c- Size
- 138394 bytes
- Lines
- 4995
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/firmware.hdrm/drm_drv.hamdgpu.hamdgpu_psp.hamdgpu_ucode.hamdgpu_xgmi.hsoc15_common.hpsp_v3_1.hpsp_v10_0.hpsp_v11_0.hpsp_v11_0_8.hpsp_v12_0.hpsp_v13_0.hpsp_v13_0_4.hpsp_v14_0.hpsp_v15_0.hpsp_v15_0_8.hamdgpu_ras.hamdgpu_securedisplay.hamdgpu_atomfirmware.h
Detected Declarations
function psp_ring_initfunction psp_check_pmfw_centralized_cstate_managementfunction psp_init_sriov_microcodefunction psp_early_initfunction IP_VERSIONfunction psp_ta_free_shared_buffunction psp_free_shared_bufsfunction psp_memory_training_finifunction psp_memory_training_initfunction psp_get_runtime_db_entryfunction psp_sw_initfunction psp_sw_finifunction psp_wait_forfunction psp_wait_for_spirom_updatefunction psp_err_warnfunction psp_cmd_submit_buffunction release_psp_cmd_buffunction psp_prep_tmr_cmd_buffunction psp_prep_load_toc_cmd_buffunction psp_load_tocfunction psp_tmr_initfunction psp_skip_tmrfunction psp_tmr_loadfunction psp_prep_tmr_unload_cmd_buffunction psp_tmr_unloadfunction psp_tmr_terminatefunction psp_get_fw_attestation_records_addrfunction psp_get_fw_reservation_infofunction psp_update_fw_reservationfunction psp_boot_config_getfunction psp_boot_config_setfunction psp_rl_loadfunction psp_memory_partitionfunction psp_ptl_fmt_verifyfunction psp_ptl_invokefunction amdgpu_ptl_perf_monitor_ctrlfunction str_to_ptl_fmtfunction ptl_supported_formats_showfunction ptl_enable_storefunction ptl_enable_showfunction ptl_format_storefunction ptl_format_showfunction amdgpu_ptl_is_visiblefunction amdgpu_ptl_sysfs_initfunction amdgpu_ptl_sysfs_finifunction psp_spatial_partitionfunction psp_asd_initializefunction psp_prep_ta_unload_cmd_buf
Annotated Snippet
static const struct file_operations psp_dump_spirom_debugfs_ops = {
.owner = THIS_MODULE,
.open = psp_read_spirom_debugfs_open,
.read = psp_read_spirom_debugfs_read,
.release = psp_read_spirom_debugfs_release,
.llseek = default_llseek,
};
#endif
void amdgpu_psp_debugfs_init(struct amdgpu_device *adev)
{
#if defined(CONFIG_DEBUG_FS)
struct drm_minor *minor = adev_to_drm(adev)->primary;
debugfs_create_file_size("psp_spirom_dump", 0444, minor->debugfs_root,
adev, &psp_dump_spirom_debugfs_ops, AMD_VBIOS_FILE_MAX_SIZE_B * 2);
#endif
}
const struct amd_ip_funcs psp_ip_funcs = {
.name = "psp",
.early_init = psp_early_init,
.sw_init = psp_sw_init,
.sw_fini = psp_sw_fini,
.hw_init = psp_hw_init,
.hw_fini = psp_hw_fini,
.suspend = psp_suspend,
.resume = psp_resume,
.set_clockgating_state = psp_set_clockgating_state,
.set_powergating_state = psp_set_powergating_state,
};
const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 3,
.minor = 1,
.rev = 0,
.funcs = &psp_ip_funcs,
};
const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 10,
.minor = 0,
.rev = 0,
.funcs = &psp_ip_funcs,
};
const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 11,
.minor = 0,
.rev = 0,
.funcs = &psp_ip_funcs,
};
const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 11,
.minor = 0,
.rev = 8,
.funcs = &psp_ip_funcs,
};
const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 12,
.minor = 0,
.rev = 0,
.funcs = &psp_ip_funcs,
};
const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 13,
.minor = 0,
.rev = 0,
.funcs = &psp_ip_funcs,
};
const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
.type = AMD_IP_BLOCK_TYPE_PSP,
.major = 13,
.minor = 0,
.rev = 4,
.funcs = &psp_ip_funcs,
};
const struct amdgpu_ip_block_version psp_v14_0_ip_block = {
.type = AMD_IP_BLOCK_TYPE_PSP,
Annotation
- Immediate include surface: `linux/firmware.h`, `drm/drm_drv.h`, `amdgpu.h`, `amdgpu_psp.h`, `amdgpu_ucode.h`, `amdgpu_xgmi.h`, `soc15_common.h`, `psp_v3_1.h`.
- Detected declarations: `function psp_ring_init`, `function psp_check_pmfw_centralized_cstate_management`, `function psp_init_sriov_microcode`, `function psp_early_init`, `function IP_VERSION`, `function psp_ta_free_shared_buf`, `function psp_free_shared_bufs`, `function psp_memory_training_fini`, `function psp_memory_training_init`, `function psp_get_runtime_db_entry`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: pattern implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.