drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c- Extension
.c- Size
- 160187 bytes
- Lines
- 5837
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu_reg_access.hlinux/debugfs.hlinux/list.hlinux/module.hlinux/uaccess.hlinux/reboot.hlinux/syscalls.hlinux/pm_runtime.hlinux/list_sort.hamdgpu.hamdgpu_ras.hamdgpu_atomfirmware.hamdgpu_xgmi.hivsrcid/nbio/irqsrcs_nbif_7_4.hnbio_v4_3.hnbif_v6_3_1.hnbio_v7_9.hatom.hamdgpu_reset.hamdgpu_psp.hamdgpu_ras_mgr.hamdgpu_virt_ras_cmd.hasm/mce.h
Detected Declarations
struct amdgpu_ras_block_liststruct mce_notifier_adev_listenum amdgpu_ras_retire_page_reservationfunction amdgpu_ras_set_error_query_readyfunction amdgpu_ras_get_error_query_readyfunction amdgpu_reserve_page_directfunction amdgpu_check_address_validityfunction amdgpu_ras_debugfs_readfunction amdgpu_ip_versionfunction amdgpu_ras_find_block_id_by_namefunction amdgpu_ras_debugfs_ctrl_parse_datafunction amdgpu_ras_instance_mask_checkfunction amdgpu_ras_debugfs_ctrl_writefunction amdgpu_ras_debugfs_eeprom_writefunction uncorrectedfunction put_objfunction amdgpu_ras_is_feature_allowedfunction amdgpu_ras_is_feature_enabledfunction __amdgpu_ras_feature_enablefunction amdgpu_ras_feature_enablefunction amdgpu_ras_feature_enable_on_bootfunction amdgpu_ras_disable_all_featuresfunction list_for_each_entry_safefunction amdgpu_ras_enable_all_featuresfunction amdgpu_ras_block_match_defaultfunction list_for_each_entry_safefunction amdgpu_ras_get_ecc_infofunction amdgpu_ras_error_print_error_datafunction for_each_ras_errorfunction for_each_ras_errorfunction for_each_ras_errorfunction for_each_ras_errorfunction err_data_has_source_infofunction amdgpu_ras_error_generate_reportfunction amdgpu_ras_virt_error_generate_reportfunction amdgpu_rasmgr_error_data_statistic_updatefunction amdgpu_ras_mgr_virt_error_data_statistics_updatefunction amdgpu_ras_bind_acafunction amdgpu_ras_unbind_acafunction amdgpu_aca_log_ras_error_datafunction amdgpu_ras_aca_sysfs_readfunction amdgpu_ras_query_error_status_helperfunction amdgpu_ras_query_error_status_with_eventfunction amdgpu_uniras_clear_badpages_infofunction amdgpu_uniras_query_block_eccfunction amdgpu_ras_query_error_statusfunction amdgpu_ras_reset_error_countfunction amdgpu_ras_reset_error_status
Annotated Snippet
static const struct file_operations amdgpu_ras_debugfs_ops = {
.owner = THIS_MODULE,
.read = amdgpu_ras_debugfs_read,
.write = NULL,
.llseek = default_llseek
};
static int amdgpu_ras_find_block_id_by_name(const char *name, int *block_id)
{
int i;
for (i = 0; i < ARRAY_SIZE(ras_block_string); i++) {
*block_id = i;
if (strcmp(name, ras_block_string[i]) == 0)
return 0;
}
return -EINVAL;
}
static int amdgpu_ras_debugfs_ctrl_parse_data(struct file *f,
const char __user *buf, size_t size,
loff_t *pos, struct ras_debug_if *data)
{
ssize_t s = min_t(u64, 64, size);
char str[65];
char block_name[33];
char err[9] = "ue";
int op = -1;
int block_id;
uint32_t sub_block;
u64 address, value;
/* default value is 0 if the mask is not set by user */
u32 instance_mask = 0;
if (*pos)
return -EINVAL;
*pos = size;
memset(str, 0, sizeof(str));
memset(data, 0, sizeof(*data));
if (copy_from_user(str, buf, s))
return -EINVAL;
if (sscanf(str, "disable %32s", block_name) == 1)
op = 0;
else if (sscanf(str, "enable %32s %8s", block_name, err) == 2)
op = 1;
else if (sscanf(str, "inject %32s %8s", block_name, err) == 2)
op = 2;
else if (strstr(str, "retire_page") != NULL)
op = 3;
else if (strstr(str, "check_address") != NULL)
op = 4;
else if (str[0] && str[1] && str[2] && str[3])
/* ascii string, but commands are not matched. */
return -EINVAL;
if (op != -1) {
if (op == 3) {
if (sscanf(str, "%*s 0x%llx", &address) != 1 &&
sscanf(str, "%*s %llu", &address) != 1)
return -EINVAL;
data->op = op;
data->inject.address = address;
return 0;
} else if (op == 4) {
if (sscanf(str, "%*s 0x%llx 0x%llx", &address, &value) != 2 &&
sscanf(str, "%*s %llu %llu", &address, &value) != 2)
return -EINVAL;
data->op = op;
data->inject.address = address;
data->inject.value = value;
return 0;
}
if (amdgpu_ras_find_block_id_by_name(block_name, &block_id))
return -EINVAL;
data->head.block = block_id;
/* only ue, ce and poison errors are supported */
if (!memcmp("ue", err, 2))
data->head.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
else if (!memcmp("ce", err, 2))
data->head.type = AMDGPU_RAS_ERROR__SINGLE_CORRECTABLE;
else if (!memcmp("poison", err, 6))
data->head.type = AMDGPU_RAS_ERROR__POISON;
Annotation
- Immediate include surface: `amdgpu_reg_access.h`, `linux/debugfs.h`, `linux/list.h`, `linux/module.h`, `linux/uaccess.h`, `linux/reboot.h`, `linux/syscalls.h`, `linux/pm_runtime.h`.
- Detected declarations: `struct amdgpu_ras_block_list`, `struct mce_notifier_adev_list`, `enum amdgpu_ras_retire_page_reservation`, `function amdgpu_ras_set_error_query_ready`, `function amdgpu_ras_get_error_query_ready`, `function amdgpu_reserve_page_direct`, `function amdgpu_check_address_validity`, `function amdgpu_ras_debugfs_read`, `function amdgpu_ip_version`, `function amdgpu_ras_find_block_id_by_name`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: pattern implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.