drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c- Extension
.c- Size
- 58466 bytes
- Lines
- 1993
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu_ras_eeprom.hamdgpu.hamdgpu_ras.hlinux/bits.hatom.hamdgpu_eeprom.hamdgpu_atomfirmware.hlinux/debugfs.hlinux/uaccess.hamdgpu_reset.hamdgpu_ras_mgr.h
Detected Declarations
function filesfunction __get_eeprom_i2c_addrfunction __encode_table_header_to_buffunction __decode_table_header_from_buffunction __write_table_headerfunction __encode_table_ras_info_to_buffunction __decode_table_ras_info_from_buffunction __write_table_ras_infofunction __calc_hdr_byte_sumfunction __calc_ras_info_byte_sumfunction amdgpu_ras_eeprom_correct_header_tagfunction amdgpu_ras_set_eeprom_table_versionfunction amdgpu_ras_eeprom_reset_tablefunction __encode_table_record_to_buffunction __decode_table_record_from_buffunction amdgpu_ras_eeprom_check_err_thresholdfunction __amdgpu_ras_eeprom_writefunction amdgpu_ras_eeprom_append_tablefunction amdgpu_ras_eeprom_update_headerfunction amdgpu_ras_eeprom_update_record_numfunction amdgpu_ras_smu_eeprom_appendfunction amdgpu_ras_eeprom_appendfunction __amdgpu_ras_eeprom_readfunction amdgpu_ras_eeprom_read_idxfunction amdgpu_ras_eeprom_readfunction amdgpu_ras_eeprom_max_record_countfunction amdgpu_ras_debugfs_eeprom_size_readfunction amdgpu_ras_debugfs_table_sizefunction amdgpu_ras_debugfs_set_ret_sizefunction amdgpu_ras_debugfs_table_readfunction amdgpu_ras_debugfs_eeprom_table_readfunction __verify_ras_table_checksumfunction __read_table_ras_infofunction amdgpu_ras_smu_eeprom_initfunction amdgpu_ras_eeprom_initfunction amdgpu_ras_smu_eeprom_checkfunction amdgpu_ras_eeprom_checkfunction amdgpu_ras_eeprom_check_and_recoverfunction amdgpu_ras_smu_get_feature_flagsfunction amdgpu_ras_smu_eeprom_supportedfunction amdgpu_ras_smu_get_table_versionfunction amdgpu_ras_smu_get_badpage_countfunction amdgpu_ras_smu_get_badpage_mca_addrfunction amdgpu_ras_smu_set_timestampfunction amdgpu_ras_smu_get_timestampfunction amdgpu_ras_smu_get_badpage_ipidfunction amdgpu_ras_smu_erase_ras_tablefunction amdgpu_ras_check_bad_page_status
Annotated Snippet
const struct file_operations amdgpu_ras_debugfs_eeprom_size_ops = {
.owner = THIS_MODULE,
.read = amdgpu_ras_debugfs_eeprom_size_read,
.write = NULL,
.llseek = default_llseek,
};
static const char *tbl_hdr_str = " Signature Version FirstOffs Size Checksum\n";
static const char *tbl_hdr_fmt = "0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n";
#define tbl_hdr_fmt_size (5 * (2+8) + 4 + 1)
static const char *rec_hdr_str = "Index Offset ErrType Bank/CU TimeStamp Offs/Addr MemChl MCUMCID RetiredPage\n";
static const char *rec_hdr_fmt = "%5d 0x%05X %7s 0x%02X 0x%016llX 0x%012llX 0x%02X 0x%02X 0x%012llX\n";
#define rec_hdr_fmt_size (5 + 1 + 7 + 1 + 7 + 1 + 7 + 1 + 18 + 1 + 14 + 1 + 6 + 1 + 7 + 1 + 14 + 1)
static const char *record_err_type_str[AMDGPU_RAS_EEPROM_ERR_COUNT] = {
"ignore",
"re",
"ue",
};
static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control)
{
return strlen(tbl_hdr_str) + tbl_hdr_fmt_size +
strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs;
}
void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control)
{
struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras,
eeprom_control);
struct dentry *de = ras->de_ras_eeprom_table;
if (de)
d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control);
}
static ssize_t amdgpu_ras_debugfs_table_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
struct amdgpu_device *adev = (struct amdgpu_device *)file_inode(f)->i_private;
struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control;
const size_t orig_size = size;
int res = -EFAULT;
size_t data_len;
/* pmfw manages eeprom data by itself */
if (amdgpu_ras_smu_eeprom_supported(adev))
return 0;
mutex_lock(&control->ras_tbl_mutex);
/* We want *pos - data_len > 0, which means there's
* bytes to be printed from data.
*/
data_len = strlen(tbl_hdr_str);
if (*pos < data_len) {
data_len -= *pos;
data_len = min_t(size_t, data_len, size);
if (copy_to_user(buf, &tbl_hdr_str[*pos], data_len))
goto Out;
buf += data_len;
size -= data_len;
*pos += data_len;
}
data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size;
if (*pos < data_len && size > 0) {
u8 data[tbl_hdr_fmt_size + 1];
loff_t lpos;
snprintf(data, sizeof(data), tbl_hdr_fmt,
control->tbl_hdr.header,
control->tbl_hdr.version,
control->tbl_hdr.first_rec_offset,
control->tbl_hdr.tbl_size,
control->tbl_hdr.checksum);
data_len -= *pos;
data_len = min_t(size_t, data_len, size);
lpos = *pos - strlen(tbl_hdr_str);
if (copy_to_user(buf, &data[lpos], data_len))
goto Out;
buf += data_len;
size -= data_len;
*pos += data_len;
}
data_len = strlen(tbl_hdr_str) + tbl_hdr_fmt_size + strlen(rec_hdr_str);
if (*pos < data_len && size > 0) {
Annotation
- Immediate include surface: `amdgpu_ras_eeprom.h`, `amdgpu.h`, `amdgpu_ras.h`, `linux/bits.h`, `atom.h`, `amdgpu_eeprom.h`, `amdgpu_atomfirmware.h`, `linux/debugfs.h`.
- Detected declarations: `function files`, `function __get_eeprom_i2c_addr`, `function __encode_table_header_to_buf`, `function __decode_table_header_from_buf`, `function __write_table_header`, `function __encode_table_ras_info_to_buf`, `function __decode_table_ras_info_from_buf`, `function __write_table_ras_info`, `function __calc_hdr_byte_sum`, `function __calc_ras_info_byte_sum`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: pattern implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.