drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h- Extension
.h- Size
- 33290 bytes
- Lines
- 1049
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/debugfs.hlinux/list.hlinux/kfifo.hlinux/radix-tree.hta_ras_if.hamdgpu_ras_eeprom.hamdgpu_smuio.hamdgpu_aca.h
Detected Declarations
struct amdgpu_iv_entrystruct amdgpu_ras_err_status_reg_entrystruct amdgpu_ras_memory_id_entrystruct ras_common_ifstruct ecc_info_per_chstruct umc_ecc_infostruct ras_event_statestruct ras_event_managerstruct ras_event_idstruct ras_query_contextstruct ras_poison_msgstruct ras_err_pagesstruct ras_ecc_errstruct ras_ecc_log_infostruct ras_critical_regionstruct ras_eeprom_table_versionstruct ras_eeprom_smu_funcsstruct ras_smu_drvstruct amdgpu_rasstruct ras_fs_datastruct ras_err_infostruct ras_err_nodestruct ras_err_datastruct ras_err_handler_datastruct ras_ih_datastruct ras_managerstruct ras_badpagestruct ras_fs_ifstruct ras_query_ifstruct ras_inject_ifstruct ras_cure_ifstruct ras_ih_ifstruct ras_dispatch_ifstruct ras_debug_ifstruct amdgpu_ras_block_objectstruct amdgpu_ras_block_hw_opsenum amdgpu_ras_blockenum amdgpu_ras_mca_blockenum amdgpu_ras_gfx_subblockenum amdgpu_ras_error_typeenum amdgpu_ras_retenum amdgpu_ras_error_query_modeenum ras_event_typeenum ras_smu_feature_flagsfunction amdgpu_ras_block_to_tafunction amdgpu_ras_error_to_tafunction amdgpu_ras_intr_triggeredfunction amdgpu_ras_intr_cleared
Annotated Snippet
struct amdgpu_ras_err_status_reg_entry {
uint32_t hwip;
uint32_t ip_inst;
uint32_t seg_lo;
uint32_t reg_lo;
uint32_t seg_hi;
uint32_t reg_hi;
uint32_t reg_inst;
uint32_t flags;
const char *block_name;
};
struct amdgpu_ras_memory_id_entry {
uint32_t memory_id;
const char *name;
};
struct ras_common_if {
enum amdgpu_ras_block block;
enum amdgpu_ras_error_type type;
uint32_t sub_block_index;
char name[32];
};
#define MAX_UMC_CHANNEL_NUM 32
struct ecc_info_per_ch {
uint16_t ce_count_lo_chip;
uint16_t ce_count_hi_chip;
uint64_t mca_umc_status;
uint64_t mca_umc_addr;
uint64_t mca_ceumc_addr;
};
struct umc_ecc_info {
struct ecc_info_per_ch ecc[MAX_UMC_CHANNEL_NUM];
/* Determine smu ecctable whether support
* record correctable error address
*/
int record_ce_addr_supported;
};
enum ras_event_type {
RAS_EVENT_TYPE_INVALID = 0,
RAS_EVENT_TYPE_FATAL,
RAS_EVENT_TYPE_POISON_CREATION,
RAS_EVENT_TYPE_POISON_CONSUMPTION,
RAS_EVENT_TYPE_COUNT,
};
struct ras_event_state {
u64 last_seqno;
atomic64_t count;
};
struct ras_event_manager {
atomic64_t seqno;
struct ras_event_state event_state[RAS_EVENT_TYPE_COUNT];
};
struct ras_event_id {
enum ras_event_type type;
u64 event_id;
};
struct ras_query_context {
struct ras_event_id evid;
};
typedef int (*pasid_notify)(struct amdgpu_device *adev,
uint16_t pasid, void *data);
struct ras_poison_msg {
enum amdgpu_ras_block block;
uint16_t pasid;
uint32_t reset;
pasid_notify pasid_fn;
void *data;
};
struct ras_err_pages {
uint32_t count;
uint64_t *pfn;
};
struct ras_ecc_err {
uint64_t status;
uint64_t ipid;
uint64_t addr;
Annotation
- Immediate include surface: `linux/debugfs.h`, `linux/list.h`, `linux/kfifo.h`, `linux/radix-tree.h`, `ta_ras_if.h`, `amdgpu_ras_eeprom.h`, `amdgpu_smuio.h`, `amdgpu_aca.h`.
- Detected declarations: `struct amdgpu_iv_entry`, `struct amdgpu_ras_err_status_reg_entry`, `struct amdgpu_ras_memory_id_entry`, `struct ras_common_if`, `struct ecc_info_per_ch`, `struct umc_ecc_info`, `struct ras_event_state`, `struct ras_event_manager`, `struct ras_event_id`, `struct ras_query_context`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.