drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
Extension
.c
Size
27600 bytes
Lines
983
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (version) {
		case 1:
			return amdgpu_reg_smn_v1_0_get_base(adev, block,
							    die_inst);
		default:
			dev_err_once(
				adev->dev,
				"SMN base address query not supported for this device\n");
			return 0;
		}
	}
	return adev->reg.smn.get_smn_base(adev, block, die_inst);
}

uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev,
				      enum amd_hw_ip_block_type block,
				      int die_inst)
{
	uint64_t smn_base;

	if (die_inst == 0)
		return 0;

	switch (block) {
	case XGMI_HWIP:
	case NBIO_HWIP:
	case MP0_HWIP:
	case UMC_HWIP:
	case DF_HWIP:
		smn_base = ((uint64_t)(die_inst & 0x3) << 32) | (1ULL << 34);
		break;
	default:
		dev_warn_once(
			adev->dev,
			"SMN base address query not supported for this block %d\n",
			block);
		smn_base = 0;
		break;
	}

	return smn_base;
}

/*
 * register access helper functions.
 */

/**
 * amdgpu_device_rreg - read a memory mapped IO or indirect register
 *
 * @adev: amdgpu_device pointer
 * @reg: dword aligned register offset
 * @acc_flags: access flags which require special behavior
 *
 * Returns the 32 bit value from the offset specified.
 */
uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
			    uint32_t acc_flags)
{
	uint32_t ret;

	if (amdgpu_device_skip_hw_access(adev))
		return 0;

	if ((reg * 4) < adev->rmmio_size) {
		if (!(acc_flags & AMDGPU_REGS_NO_KIQ) &&
		    amdgpu_sriov_runtime(adev) &&
		    down_read_trylock(&adev->reset_domain->sem)) {
			ret = amdgpu_kiq_rreg(adev, reg, 0);
			up_read(&adev->reset_domain->sem);
		} else {
			ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
		}
	} else {
		ret = amdgpu_reg_pcie_rd32(adev, reg * 4);
	}

	trace_amdgpu_device_rreg(adev->pdev->device, reg, ret);

	return ret;
}

/*
 * MMIO register read with bytes helper functions
 * @offset:bytes offset from MMIO start
 */

/**
 * amdgpu_mm_rreg8 - read a memory mapped IO register
 *

Annotation

Implementation Notes