drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
Extension
.h
Size
14698 bytes
Lines
378
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct amdgpu_rlc_funcs {
	bool (*is_rlc_enabled)(struct amdgpu_device *adev);
	void (*set_safe_mode)(struct amdgpu_device *adev, int xcc_id);
	void (*unset_safe_mode)(struct amdgpu_device *adev, int xcc_id);
	int  (*init)(struct amdgpu_device *adev);
	u32  (*get_csb_size)(struct amdgpu_device *adev);

	/**
	 * @get_csb_buffer: Get the clear state to be put into the hardware.
	 *
	 * The parameter adev is used to get the CS data and other gfx info,
	 * and buffer is the RLC CS pointer
	 *
	 * Sometimes, the user space puts a request to clear the state in the
	 * command buffer; this function provides the clear state that gets put
	 * into the hardware. Note that the driver programs Clear State
	 * Indirect Buffer (CSB) explicitly when it sets up the kernel rings,
	 * and it also provides a pointer to it which is used by the firmware
	 * to load the clear state in some cases.
	 */
	void (*get_csb_buffer)(struct amdgpu_device *adev, u32 *buffer);
	int  (*get_cp_table_num)(struct amdgpu_device *adev);
	int  (*resume)(struct amdgpu_device *adev);
	void (*stop)(struct amdgpu_device *adev);
	void (*reset)(struct amdgpu_device *adev);
	void (*start)(struct amdgpu_device *adev);
	void (*update_spm_vmid)(struct amdgpu_device *adev, int xcc_id,
			struct amdgpu_ring *ring, unsigned vmid);
	bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t reg);
};

struct amdgpu_rlcg_reg_access_ctrl {
	uint32_t scratch_reg0;
	uint32_t scratch_reg1;
	uint32_t scratch_reg2;
	uint32_t scratch_reg3;
	uint32_t grbm_cntl;
	uint32_t grbm_idx;
	uint32_t spare_int;

	uint32_t vfi_cmd;
	uint32_t vfi_stat;
	uint32_t vfi_addr;
	uint32_t vfi_data;
	uint32_t vfi_grbm_cntl;
	uint32_t vfi_grbm_idx;
	uint32_t vfi_grbm_cntl_data;
	uint32_t vfi_grbm_idx_data;
};

struct amdgpu_rlc {
	/* for power gating */
	struct amdgpu_bo        *save_restore_obj;
	uint64_t                save_restore_gpu_addr;
	uint32_t		*sr_ptr;
	const u32               *reg_list;
	u32                     reg_list_size;
	/* for clear state */
	struct amdgpu_bo        *clear_state_obj;
	uint64_t                clear_state_gpu_addr;
	uint32_t		*cs_ptr;
	const struct cs_section_def   *cs_data;
	u32                     clear_state_size;
	/* for cp tables */
	struct amdgpu_bo        *cp_table_obj;
	uint64_t                cp_table_gpu_addr;
	uint32_t		*cp_table_ptr;
	u32                     cp_table_size;

	/* safe mode for updating CG/PG state */
	bool in_safe_mode[AMDGPU_MAX_RLC_INSTANCES];
	const struct amdgpu_rlc_funcs *funcs;

	/* for firmware data */
	u32 save_and_restore_offset;
	u32 clear_state_descriptor_offset;
	u32 avail_scratch_ram_locations;
	u32 reg_restore_list_size;
	u32 reg_list_format_start;
	u32 reg_list_format_separate_start;
	u32 starting_offsets_start;
	u32 reg_list_format_size_bytes;
	u32 reg_list_size_bytes;
	u32 reg_list_format_direct_reg_list_length;
	u32 save_restore_list_cntl_size_bytes;
	u32 save_restore_list_gpm_size_bytes;
	u32 save_restore_list_srm_size_bytes;
	u32 rlc_iram_ucode_size_bytes;
	u32 rlc_dram_ucode_size_bytes;
	u32 rlc_1_iram_ucode_size_bytes;

Annotation

Implementation Notes