drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
Extension
.h
Size
7092 bytes
Lines
218
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct amdgpu_sdma_csa_info {
	u32 size;
	u32 alignment;
};

struct amdgpu_sdma_funcs {
	int (*stop_kernel_queue)(struct amdgpu_ring *ring);
	int (*start_kernel_queue)(struct amdgpu_ring *ring);
	int (*soft_reset_kernel_queue)(struct amdgpu_device *adev, u32 instance_id);
};

struct amdgpu_sdma_instance {
	/* SDMA firmware */
	const struct firmware	*fw;
	uint32_t		fw_version;
	uint32_t		feature_version;

	struct amdgpu_ring	ring;
	struct amdgpu_ring	page;
	bool			burst_nop;
	union {
	    uint32_t		aid_id;
	    uint32_t		xcc_id;
	};

	struct amdgpu_bo	*sdma_fw_obj;
	uint64_t		sdma_fw_gpu_addr;
	uint32_t		*sdma_fw_ptr;
	struct mutex		engine_reset_mutex;
	/* track guilty state of GFX and PAGE queues */
	bool			gfx_guilty;
	bool			page_guilty;
	const struct amdgpu_sdma_funcs   *funcs;
};

enum amdgpu_sdma_ras_memory_id {
	AMDGPU_SDMA_MBANK_DATA_BUF0 = 1,
	AMDGPU_SDMA_MBANK_DATA_BUF1 = 2,
	AMDGPU_SDMA_MBANK_DATA_BUF2 = 3,
	AMDGPU_SDMA_MBANK_DATA_BUF3 = 4,
	AMDGPU_SDMA_MBANK_DATA_BUF4 = 5,
	AMDGPU_SDMA_MBANK_DATA_BUF5 = 6,
	AMDGPU_SDMA_MBANK_DATA_BUF6 = 7,
	AMDGPU_SDMA_MBANK_DATA_BUF7 = 8,
	AMDGPU_SDMA_MBANK_DATA_BUF8 = 9,
	AMDGPU_SDMA_MBANK_DATA_BUF9 = 10,
	AMDGPU_SDMA_MBANK_DATA_BUF10 = 11,
	AMDGPU_SDMA_MBANK_DATA_BUF11 = 12,
	AMDGPU_SDMA_MBANK_DATA_BUF12 = 13,
	AMDGPU_SDMA_MBANK_DATA_BUF13 = 14,
	AMDGPU_SDMA_MBANK_DATA_BUF14 = 15,
	AMDGPU_SDMA_MBANK_DATA_BUF15 = 16,
	AMDGPU_SDMA_UCODE_BUF = 17,
	AMDGPU_SDMA_RB_CMD_BUF = 18,
	AMDGPU_SDMA_IB_CMD_BUF = 19,
	AMDGPU_SDMA_UTCL1_RD_FIFO = 20,
	AMDGPU_SDMA_UTCL1_RDBST_FIFO = 21,
	AMDGPU_SDMA_UTCL1_WR_FIFO = 22,
	AMDGPU_SDMA_DATA_LUT_FIFO = 23,
	AMDGPU_SDMA_SPLIT_DAT_BUF = 24,
	AMDGPU_SDMA_MEMORY_BLOCK_LAST,
};

struct amdgpu_sdma_ras {
	struct amdgpu_ras_block_object ras_block;
};

struct amdgpu_sdma {
	struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
	struct amdgpu_irq_src	trap_irq;
	struct amdgpu_irq_src	illegal_inst_irq;
	struct amdgpu_irq_src	fence_irq;
	struct amdgpu_irq_src	ecc_irq;
	struct amdgpu_irq_src	vm_hole_irq;
	struct amdgpu_irq_src	doorbell_invalid_irq;
	struct amdgpu_irq_src	pool_timeout_irq;
	struct amdgpu_irq_src	srbm_write_irq;
	struct amdgpu_irq_src	ctxt_empty_irq;

	int			num_instances;
	uint32_t 		sdma_mask;
	union {
	    int			num_inst_per_aid;
	    int			num_inst_per_xcc;
	};
	uint32_t                    srbm_soft_reset;
	bool			has_page_queue;
	struct ras_common_if	*ras_if;
	struct amdgpu_sdma_ras	*ras;
	uint32_t		*ip_dump;

Annotation

Implementation Notes