drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c- Extension
.c- Size
- 80518 bytes
- Lines
- 2917
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: operation-table or driver-model contract
- Status
- pattern implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines an operation table; this is where Linux turns generic core objects into subsystem-specific behavior.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/dma-mapping.hlinux/iommu.hlinux/pagemap.hlinux/sched/task.hlinux/sched/mm.hlinux/seq_file.hlinux/slab.hlinux/swap.hlinux/dma-buf.hlinux/sizes.hlinux/module.hdrm/drm_drv.hdrm/ttm/ttm_bo.hdrm/ttm/ttm_placement.hdrm/ttm/ttm_range_manager.hdrm/ttm/ttm_tt.hdrm/amdgpu_drm.hamdgpu.hamdgpu_object.hamdgpu_trace.hamdgpu_amdkfd.hamdgpu_sdma.hamdgpu_ras.hamdgpu_hmm.hamdgpu_atomfirmware.hamdgpu_res_cursor.hbif/bif_4_1_d.h
Detected Declarations
struct amdgpu_ttm_ttfunction amdgpu_ttm_init_on_chipfunction ttm_bo_evictfunction amdgpu_res_cpu_visiblefunction amdgpu_ttm_job_submitfunction amdgpu_ttm_map_bufferfunction amdgpu_ttm_copy_mem_to_memfunction amdgpu_bo_movefunction amdgpu_res_cpu_visiblefunction amdgpu_bo_movefunction ttm_bo_handle_move_memfunction ttm_mem_io_reservefunction amdgpu_ttm_io_mem_pfnfunction amdgpu_ttm_domain_startfunction amdgpu_ttm_tt_userptr_range_donefunction amdgpu_cs_list_validatefunction amdgpu_ttm_backend_bindfunction amdgpu_ttm_tt_unpin_userptrfunction amdgpu_ttm_gart_bind_gfx9_mqdfunction amdgpu_ttm_gart_bindfunction ttm_tt_bindfunction amdgpu_ttm_alloc_gartfunction amdgpu_gtt_mgr_recoverfunction ttm_tt_unbindfunction amdgpu_ttm_backend_destroyfunction pagefunction amdgpu_ttm_mmio_remap_free_sgtfunction ttm_tt_createfunction amdgpu_ttm_tt_populatefunction amdgpu_ttm_tt_unpopulatefunction amdgpu_ttm_tt_get_userptrfunction amdgpu_gem_userptr_ioctlfunction amdgpu_ttm_tt_affect_userptrfunction amdgpu_ttm_tt_is_userptrfunction amdgpu_ttm_tt_is_readonlyfunction PDEfunction PTEfunction ttm_bo_mem_force_spacefunction amdgpu_ttm_vram_mm_accessfunction amdgpu_ttm_access_memory_sdmafunction amdgpu_ttm_access_memoryfunction amdgpu_bo_delete_mem_notifyfunction amdgpu_ttm_init_vram_resvfunction amdgpu_ttm_init_fw_resv_regionfunction amdgpu_ttm_init_mem_train_resv_regionfunction amdgpu_ttm_init_vram_resv_regionsfunction amdgpu_ttm_mark_vram_reservedfunction amdgpu_ttm_unmark_vram_reserved
Annotated Snippet
static const struct file_operations amdgpu_ttm_vram_fops = {
.owner = THIS_MODULE,
.read = amdgpu_ttm_vram_read,
.write = amdgpu_ttm_vram_write,
.llseek = default_llseek,
};
/*
* amdgpu_iomem_read - Virtual read access to GPU mapped memory
*
* This function is used to read memory that has been mapped to the
* GPU and the known addresses are not physical addresses but instead
* bus addresses (e.g., what you'd put in an IB or ring buffer).
*/
static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
struct amdgpu_device *adev = file_inode(f)->i_private;
struct iommu_domain *dom;
ssize_t result = 0;
int r;
/* retrieve the IOMMU domain if any for this device */
dom = iommu_get_domain_for_dev(adev->dev);
while (size) {
phys_addr_t addr = *pos & PAGE_MASK;
loff_t off = *pos & ~PAGE_MASK;
size_t bytes = PAGE_SIZE - off;
unsigned long pfn;
struct page *p;
void *ptr;
bytes = min(bytes, size);
/* Translate the bus address to a physical address. If
* the domain is NULL it means there is no IOMMU active
* and the address translation is the identity
*/
addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
pfn = addr >> PAGE_SHIFT;
if (!pfn_valid(pfn))
return -EPERM;
p = pfn_to_page(pfn);
if (p->mapping != adev->mman.bdev.dev_mapping)
return -EPERM;
ptr = kmap_local_page(p);
r = copy_to_user(buf, ptr + off, bytes);
kunmap_local(ptr);
if (r)
return -EFAULT;
size -= bytes;
*pos += bytes;
result += bytes;
}
return result;
}
/*
* amdgpu_iomem_write - Virtual write access to GPU mapped memory
*
* This function is used to write memory that has been mapped to the
* GPU and the known addresses are not physical addresses but instead
* bus addresses (e.g., what you'd put in an IB or ring buffer).
*/
static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
size_t size, loff_t *pos)
{
struct amdgpu_device *adev = file_inode(f)->i_private;
struct iommu_domain *dom;
ssize_t result = 0;
int r;
dom = iommu_get_domain_for_dev(adev->dev);
while (size) {
phys_addr_t addr = *pos & PAGE_MASK;
loff_t off = *pos & ~PAGE_MASK;
size_t bytes = PAGE_SIZE - off;
unsigned long pfn;
struct page *p;
void *ptr;
bytes = min(bytes, size);
Annotation
- Immediate include surface: `linux/dma-mapping.h`, `linux/iommu.h`, `linux/pagemap.h`, `linux/sched/task.h`, `linux/sched/mm.h`, `linux/seq_file.h`, `linux/slab.h`, `linux/swap.h`.
- Detected declarations: `struct amdgpu_ttm_tt`, `function amdgpu_ttm_init_on_chip`, `function ttm_bo_evict`, `function amdgpu_res_cpu_visible`, `function amdgpu_ttm_job_submit`, `function amdgpu_ttm_map_buffer`, `function amdgpu_ttm_copy_mem_to_mem`, `function amdgpu_bo_move`, `function amdgpu_res_cpu_visible`, `function amdgpu_bo_move`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: pattern implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.