drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h- Extension
.h- Size
- 21072 bytes
- Lines
- 655
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu_socbb.h
Detected Declarations
struct common_firmware_headerstruct mc_firmware_header_v1_0struct smc_firmware_header_v1_0struct smc_firmware_header_v2_0struct smc_soft_pptable_entrystruct smc_firmware_header_v2_1struct psp_fw_legacy_bin_descstruct psp_firmware_header_v1_0struct psp_firmware_header_v1_1struct psp_firmware_header_v1_2struct psp_firmware_header_v1_3struct psp_fw_bin_descstruct psp_firmware_header_v2_0struct psp_firmware_header_v2_1struct ta_firmware_header_v1_0struct ta_firmware_header_v2_0struct gfx_firmware_header_v1_0struct gfx_firmware_header_v2_0struct mes_firmware_header_v1_0struct rlc_firmware_header_v1_0struct rlc_firmware_header_v2_0struct rlc_firmware_header_v2_1struct rlc_firmware_header_v2_2struct rlc_firmware_header_v2_3struct rlc_firmware_header_v2_4struct rlc_firmware_header_v2_5struct sdma_firmware_header_v1_0struct sdma_firmware_header_v1_1struct sdma_firmware_header_v2_0struct vpe_firmware_header_v1_0struct umsch_mm_firmware_header_v1_0struct sdma_firmware_header_v3_0struct gpu_info_firmware_v1_0struct gpu_info_firmware_v1_1struct gpu_info_firmware_v1_2struct gpu_info_firmware_header_v1_0struct dmcu_firmware_header_v1_0struct dmcub_firmware_header_v1_0struct imu_firmware_header_v1_0struct amdgpu_firmware_infostruct amdgpu_firmwarestruct kicker_deviceenum psp_fw_typeenum ta_fw_typeenum AMDGPU_UCODE_IDenum AMDGPU_UCODE_STATUSenum amdgpu_firmware_load_typeenum amdgpu_ucode_required
Annotated Snippet
struct common_firmware_header {
uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
uint32_t header_size_bytes; /* size of just the header in bytes */
uint16_t header_version_major; /* header version */
uint16_t header_version_minor; /* header version */
uint16_t ip_version_major; /* IP version */
uint16_t ip_version_minor; /* IP version */
uint32_t ucode_version;
uint32_t ucode_size_bytes; /* size of ucode in bytes */
uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
uint32_t crc32; /* crc32 checksum of the payload */
};
/* version_major=1, version_minor=0 */
struct mc_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t io_debug_size_bytes; /* size of debug array in dwords */
uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
};
/* version_major=1, version_minor=0 */
struct smc_firmware_header_v1_0 {
struct common_firmware_header header;
uint32_t ucode_start_addr;
};
/* version_major=2, version_minor=0 */
struct smc_firmware_header_v2_0 {
struct smc_firmware_header_v1_0 v1_0;
uint32_t ppt_offset_bytes; /* soft pptable offset */
uint32_t ppt_size_bytes; /* soft pptable size */
};
struct smc_soft_pptable_entry {
uint32_t id;
uint32_t ppt_offset_bytes;
uint32_t ppt_size_bytes;
};
/* version_major=2, version_minor=1 */
struct smc_firmware_header_v2_1 {
struct smc_firmware_header_v1_0 v1_0;
uint32_t pptable_count;
uint32_t pptable_entry_offset;
};
struct psp_fw_legacy_bin_desc {
uint32_t fw_version;
uint32_t offset_bytes;
uint32_t size_bytes;
};
/* version_major=1, version_minor=0 */
struct psp_firmware_header_v1_0 {
struct common_firmware_header header;
struct psp_fw_legacy_bin_desc sos;
};
/* version_major=1, version_minor=1 */
struct psp_firmware_header_v1_1 {
struct psp_firmware_header_v1_0 v1_0;
struct psp_fw_legacy_bin_desc toc;
struct psp_fw_legacy_bin_desc kdb;
};
/* version_major=1, version_minor=2 */
struct psp_firmware_header_v1_2 {
struct psp_firmware_header_v1_0 v1_0;
struct psp_fw_legacy_bin_desc res;
struct psp_fw_legacy_bin_desc kdb;
};
/* version_major=1, version_minor=3 */
struct psp_firmware_header_v1_3 {
struct psp_firmware_header_v1_1 v1_1;
struct psp_fw_legacy_bin_desc spl;
struct psp_fw_legacy_bin_desc rl;
struct psp_fw_legacy_bin_desc sys_drv_aux;
struct psp_fw_legacy_bin_desc sos_aux;
};
struct psp_fw_bin_desc {
uint32_t fw_type;
uint32_t fw_version;
uint32_t offset_bytes;
uint32_t size_bytes;
};
enum psp_fw_type {
PSP_FW_TYPE_UNKOWN,
Annotation
- Immediate include surface: `amdgpu_socbb.h`.
- Detected declarations: `struct common_firmware_header`, `struct mc_firmware_header_v1_0`, `struct smc_firmware_header_v1_0`, `struct smc_firmware_header_v2_0`, `struct smc_soft_pptable_entry`, `struct smc_firmware_header_v2_1`, `struct psp_fw_legacy_bin_desc`, `struct psp_firmware_header_v1_0`, `struct psp_firmware_header_v1_1`, `struct psp_firmware_header_v1_2`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.