drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
Extension
.h
Size
19217 bytes
Lines
574
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct dpg_pause_state {
	enum internal_dpg_state fw_based;
	enum internal_dpg_state jpeg;
};

struct amdgpu_vcn_reg{
	unsigned	data0;
	unsigned	data1;
	unsigned	cmd;
	unsigned	nop;
	unsigned	context_id;
	unsigned	ib_vmid;
	unsigned	ib_bar_low;
	unsigned	ib_bar_high;
	unsigned	ib_size;
	unsigned	gp_scratch8;
	unsigned	scratch9;
};

struct amdgpu_vcn_fw_shared {
	void        *cpu_addr;
	uint64_t    gpu_addr;
	uint32_t    mem_size;
	uint32_t    log_offset;
};

struct amdgpu_vcn_inst {
	struct amdgpu_device	*adev;
	int			inst;
	struct amdgpu_bo	*vcpu_bo;
	void			*cpu_addr;
	uint64_t		gpu_addr;
	void			*saved_bo;
	struct amdgpu_ring	ring_dec;
	struct amdgpu_ring	ring_enc[AMDGPU_VCN_MAX_ENC_RINGS];
	atomic_t		sched_score;
	struct amdgpu_irq_src	irq;
	struct amdgpu_irq_src	ras_poison_irq;
	struct amdgpu_vcn_reg	external;
	struct amdgpu_bo	*dpg_sram_bo;
	struct dpg_pause_state	pause_state;
	void			*dpg_sram_cpu_addr;
	uint64_t		dpg_sram_gpu_addr;
	uint32_t		*dpg_sram_curr_addr;
	atomic_t		dpg_enc_submission_cnt;
	struct amdgpu_vcn_fw_shared fw_shared;
	uint8_t			aid_id;
	const struct firmware	*fw; /* VCN firmware */
	uint8_t			vcn_config;
	uint32_t		vcn_codec_disable_mask;
	atomic_t		total_submission_cnt;
	struct mutex		vcn_pg_lock;
	enum amd_powergating_state cur_state;
	struct delayed_work	idle_work;
	unsigned		fw_version;
	unsigned		num_enc_rings;
	bool			indirect_sram;
	struct amdgpu_vcn_reg	 internal;
	struct mutex		vcn1_jpeg1_workaround;
	int (*pause_dpg_mode)(struct amdgpu_vcn_inst *vinst,
			      struct dpg_pause_state *new_state);
	int (*set_pg_state)(struct amdgpu_vcn_inst *vinst,
			    enum amd_powergating_state state);
	int (*reset)(struct amdgpu_vcn_inst *vinst);
	bool using_unified_queue;
	struct mutex		engine_reset_mutex;
};

struct amdgpu_vcn_ras {
	struct amdgpu_ras_block_object ras_block;
};

struct amdgpu_vcn {
	uint8_t	num_vcn_inst;
	struct amdgpu_vcn_inst	 inst[AMDGPU_MAX_VCN_INSTANCES];

	unsigned	harvest_config;

	struct ras_common_if    *ras_if;
	struct amdgpu_vcn_ras   *ras;

	uint16_t inst_mask;
	uint8_t	num_inst_per_aid;

	/* IP reg dump */
	uint32_t		*ip_dump;

	uint32_t		supported_reset;
	uint32_t		caps;

Annotation

Implementation Notes