drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c- Extension
.c- Size
- 63294 bytes
- Lines
- 2092
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hasm/hypervisor.hdrm/drm_drv.hxen/xen.hamdgpu.hamdgpu_ras.hamdgpu_reset.hamdgpu_dpm.hvi.hsoc15.hnv.hamdgpu_virt_ras_cmd.h
Detected Declarations
function amdgpu_virt_mmio_blockedfunction amdgpu_virt_init_settingfunction amdgpu_virt_request_full_gpufunction amdgpu_virt_release_full_gpufunction amdgpu_virt_reset_gpufunction amdgpu_virt_request_init_datafunction amdgpu_virt_ready_to_resetfunction amdgpu_virt_wait_resetfunction amdgpu_virt_alloc_mm_tablefunction amdgpu_virt_free_mm_tablefunction amdgpu_virt_rcvd_ras_interruptfunction amd_sriov_msg_checksumfunction amdgpu_virt_ras_realloc_eh_data_spacefunction amdgpu_virt_init_ras_err_handler_datafunction amdgpu_virt_ras_release_bpfunction amdgpu_virt_release_ras_err_handler_datafunction amdgpu_virt_ras_add_bpsfunction amdgpu_virt_ras_reserve_bpsfunction amdgpu_virt_ras_check_bad_pagefunction amdgpu_virt_add_bad_pagefunction amdgpu_virt_read_pf2vf_datafunction amdgpu_virt_populate_vf2pf_ucode_infofunction amdgpu_virt_write_vf2pf_datafunction amdgpu_virt_update_vf2pf_work_itemfunction amdgpu_virt_read_exchange_data_from_memfunction amdgpu_virt_fini_data_exchangefunction amdgpu_virt_init_data_exchangefunction amdgpu_virt_exchange_datafunction amdgpu_virt_init_detect_asicfunction amdgpu_virt_init_req_datafunction amdgpu_virt_init_rasfunction amdgpu_virt_crit_region_calc_checksumfunction amdgpu_virt_init_critical_regionfunction amdgpu_virt_get_dynamic_data_infofunction amdgpu_virt_initfunction amdgpu_virt_access_debugfs_is_mmiofunction amdgpu_virt_access_debugfs_is_kiqfunction amdgpu_virt_enable_access_debugfsfunction amdgpu_virt_disable_access_debugfsfunction amdgpu_virt_get_sriov_vf_modefunction amdgpu_virt_pre_resetfunction amdgpu_virt_post_resetfunction amdgpu_virt_fw_load_skip_checkfunction amdgpu_virt_update_sriov_video_codecfunction amdgpu_virt_get_rlcg_reg_access_flagfunction amdgpu_virt_rlcg_vfi_reg_rwfunction amdgpu_virt_rlcg_reg_rwfunction amdgpu_sriov_wreg
Annotated Snippet
if (r) {
adev->no_hw_access = true;
return r;
}
adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
}
return 0;
}
/**
* amdgpu_virt_release_full_gpu() - release full gpu access
* @adev: amdgpu device.
* @init: is driver init time.
* When finishing driver init/fini, need to release full gpu access.
* Return: Zero if release success, otherwise will returen error.
*/
int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
{
struct amdgpu_virt *virt = &adev->virt;
int r;
if (virt->ops && virt->ops->rel_full_gpu) {
r = virt->ops->rel_full_gpu(adev, init);
if (r)
return r;
adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
}
return 0;
}
/**
* amdgpu_virt_reset_gpu() - reset gpu
* @adev: amdgpu device.
* Send reset command to GPU hypervisor to reset GPU that VM is using
* Return: Zero if reset success, otherwise will return error.
*/
int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
{
struct amdgpu_virt *virt = &adev->virt;
int r;
if (virt->ops && virt->ops->reset_gpu) {
r = virt->ops->reset_gpu(adev);
if (r)
return r;
adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
}
return 0;
}
void amdgpu_virt_request_init_data(struct amdgpu_device *adev)
{
struct amdgpu_virt *virt = &adev->virt;
if (virt->ops && virt->ops->req_init_data)
virt->ops->req_init_data(adev);
if (adev->virt.req_init_data_ver > 0)
dev_info(adev->dev, "host supports REQ_INIT_DATA handshake of critical_region_version %d\n",
adev->virt.req_init_data_ver);
else
dev_warn(adev->dev, "host doesn't support REQ_INIT_DATA handshake\n");
}
/**
* amdgpu_virt_ready_to_reset() - send ready to reset to host
* @adev: amdgpu device.
* Send ready to reset message to GPU hypervisor to signal we have stopped GPU
* activity and is ready for host FLR
*/
void amdgpu_virt_ready_to_reset(struct amdgpu_device *adev)
{
struct amdgpu_virt *virt = &adev->virt;
if (virt->ops && virt->ops->reset_gpu)
virt->ops->ready_to_reset(adev);
}
/**
* amdgpu_virt_wait_reset() - wait for reset gpu completed
* @adev: amdgpu device.
* Wait for GPU reset completed.
* Return: Zero if reset success, otherwise will return error.
*/
int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
Annotation
- Immediate include surface: `linux/module.h`, `asm/hypervisor.h`, `drm/drm_drv.h`, `xen/xen.h`, `amdgpu.h`, `amdgpu_ras.h`, `amdgpu_reset.h`, `amdgpu_dpm.h`.
- Detected declarations: `function amdgpu_virt_mmio_blocked`, `function amdgpu_virt_init_setting`, `function amdgpu_virt_request_full_gpu`, `function amdgpu_virt_release_full_gpu`, `function amdgpu_virt_reset_gpu`, `function amdgpu_virt_request_init_data`, `function amdgpu_virt_ready_to_reset`, `function amdgpu_virt_wait_reset`, `function amdgpu_virt_alloc_mm_table`, `function amdgpu_virt_free_mm_table`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.