drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
Extension
.h
Size
18762 bytes
Lines
510
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct amdgpu_mm_table {
	struct amdgpu_bo	*bo;
	uint32_t		*cpu_addr;
	uint64_t		gpu_addr;
};

#define AMDGPU_VF_ERROR_ENTRY_SIZE    16

/* struct error_entry - amdgpu VF error information. */
struct amdgpu_vf_error_buffer {
	struct mutex lock;
	int read_count;
	int write_count;
	uint16_t code[AMDGPU_VF_ERROR_ENTRY_SIZE];
	uint16_t flags[AMDGPU_VF_ERROR_ENTRY_SIZE];
	uint64_t data[AMDGPU_VF_ERROR_ENTRY_SIZE];
};

enum idh_request;

/**
 * struct amdgpu_virt_ops - amdgpu device virt operations
 */
struct amdgpu_virt_ops {
	int (*req_full_gpu)(struct amdgpu_device *adev, bool init);
	int (*rel_full_gpu)(struct amdgpu_device *adev, bool init);
	int (*req_init_data)(struct amdgpu_device *adev);
	int (*reset_gpu)(struct amdgpu_device *adev);
	void (*ready_to_reset)(struct amdgpu_device *adev);
	int (*wait_reset)(struct amdgpu_device *adev);
	void (*trans_msg)(struct amdgpu_device *adev, enum idh_request req,
			  u32 data1, u32 data2, u32 data3);
	void (*ras_poison_handler)(struct amdgpu_device *adev,
					enum amdgpu_ras_block block);
	bool (*rcvd_ras_intr)(struct amdgpu_device *adev);
	int (*req_ras_err_count)(struct amdgpu_device *adev);
	int (*req_ras_cper_dump)(struct amdgpu_device *adev, u64 vf_rptr);
	int (*req_bad_pages)(struct amdgpu_device *adev);
	int (*req_ras_chk_criti)(struct amdgpu_device *adev, u64 addr);
	int (*req_remote_ras_cmd)(struct amdgpu_device *adev,
			u32 param1, u32 param2, u32 param3);
};

/*
 * Firmware Reserve Frame buffer
 */
struct amdgpu_virt_fw_reserve {
	struct amd_sriov_msg_pf2vf_info_header *p_pf2vf;
	struct amd_sriov_msg_vf2pf_info_header *p_vf2pf;
	void *ras_telemetry;
	unsigned int checksum_key;
};

/*
 * Legacy GIM header
 *
 * Defination between PF and VF
 * Structures forcibly aligned to 4 to keep the same style as PF.
 */
#define AMDGIM_DATAEXCHANGE_OFFSET		(64 * 1024)

#define AMDGIM_GET_STRUCTURE_RESERVED_SIZE(total, u8, u16, u32, u64) \
		(total - (((u8)+3) / 4 + ((u16)+1) / 2 + (u32) + (u64)*2))

enum AMDGIM_FEATURE_FLAG {
	/* GIM supports feature of Error log collecting */
	AMDGIM_FEATURE_ERROR_LOG_COLLECT = 0x1,
	/* GIM supports feature of loading uCodes */
	AMDGIM_FEATURE_GIM_LOAD_UCODES   = 0x2,
	/* VRAM LOST by GIM */
	AMDGIM_FEATURE_GIM_FLR_VRAMLOST = 0x4,
	/* MM bandwidth */
	AMDGIM_FEATURE_GIM_MM_BW_MGR = 0x8,
	/* PP ONE VF MODE in GIM */
	AMDGIM_FEATURE_PP_ONE_VF = (1 << 4),
	/* Indirect Reg Access enabled */
	AMDGIM_FEATURE_INDIRECT_REG_ACCESS = (1 << 5),
	/* AV1 Support MODE*/
	AMDGIM_FEATURE_AV1_SUPPORT = (1 << 6),
	/* VCN RB decouple */
	AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7),
	/* MES info */
	AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8),
	AMDGIM_FEATURE_RAS_CAPS = (1 << 9),
	AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10),
	AMDGIM_FEATURE_RAS_CPER = (1 << 11),
	AMDGIM_FEATURE_XGMI_TA_EXT_PEER_LINK = (1 << 12),
	AMDGIM_FEATURE_XGMI_CONNECTED_TO_CPU = (1 << 13),
	AMDGIM_FEATURE_PTL_SUPPORT = (1 << 14),
	AMDGIM_FEATURE_UNITID_SUPPORT = (1 << 15),

Annotation

Implementation Notes