drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
Extension
.h
Size
23163 bytes
Lines
699
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct amdgpu_vm_bo_base {
	/* constant after initialization */
	struct amdgpu_vm		*vm;
	struct amdgpu_bo		*bo;

	/* protected by bo being reserved */
	struct amdgpu_vm_bo_base	*next;

	/* protected by vm reservation and invalidated_lock */
	struct list_head		vm_status;

	/* if the bo is counted as shared in mem stats
	 * protected by vm BO being reserved */
	bool				shared;

	/* protected by the BO being reserved */
	bool				moved;
};

/*
 * The following status lists contain amdgpu_vm_bo_base objects for
 * either PD/PTs, per VM BOs or BOs with individual resv object.
 *
 * The state transits are: evicted -> moved -> idle
 */
struct amdgpu_vm_bo_status {
	/* BOs evicted which need to move into place again */
	struct list_head		evicted;

	/* BOs which moved but new location hasn't been updated in the PDs/PTs */
	struct list_head		moved;

	/* BOs done with the state machine and need no further action */
	struct list_head		idle;
};

/* provided by hw blocks that can write ptes, e.g., sdma */
struct amdgpu_vm_pte_funcs {
	/* number of dw to reserve per operation */
	unsigned	copy_pte_num_dw;

	/* copy pte entries from GART */
	void (*copy_pte)(struct amdgpu_ib *ib,
			 uint64_t pe, uint64_t src,
			 unsigned count);

	/* write pte one entry at a time with addr mapping */
	void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
			  uint64_t value, unsigned count,
			  uint32_t incr);
	/* for linear pte/pde updates without addr mapping */
	void (*set_pte_pde)(struct amdgpu_ib *ib,
			    uint64_t pe,
			    uint64_t addr, unsigned count,
			    uint32_t incr, uint64_t flags);
};

struct amdgpu_task_info {
	struct drm_wedge_task_info task;
	char		process_name[TASK_COMM_LEN];
	pid_t		tgid;
	struct kref	refcount;
};

/**
 * struct amdgpu_vm_update_params
 *
 * Encapsulate some VM table update parameters to reduce
 * the number of function parameters
 *
 */
struct amdgpu_vm_update_params {

	/**
	 * @adev: amdgpu device we do this update for
	 */
	struct amdgpu_device *adev;

	/**
	 * @vm: optional amdgpu_vm we do this update for
	 */
	struct amdgpu_vm *vm;

	/**
	 * @immediate: if changes should be made immediately
	 */
	bool immediate;

	/**
	 * @unlocked: true if the root BO is not locked

Annotation

Implementation Notes