drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c
Extension
.c
Size
3245 bytes
Lines
112
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct amdgpu_tlb_fence {
	struct dma_fence	base;
	struct amdgpu_device	*adev;
	struct dma_fence	*dependency;
	struct work_struct	work;
	spinlock_t		lock;
	uint16_t		pasid;

};

static const char *amdgpu_tlb_fence_get_driver_name(struct dma_fence *fence)
{
	return "amdgpu tlb fence";
}

static const char *amdgpu_tlb_fence_get_timeline_name(struct dma_fence *f)
{
	return "amdgpu tlb timeline";
}

static void amdgpu_tlb_fence_work(struct work_struct *work)
{
	struct amdgpu_tlb_fence *f = container_of(work, typeof(*f), work);
	int r;

	if (f->dependency) {
		dma_fence_wait(f->dependency, false);
		dma_fence_put(f->dependency);
		f->dependency = NULL;
	}

	r = amdgpu_gmc_flush_gpu_tlb_pasid(f->adev, f->pasid, 2, true, 0);
	if (r) {
		dev_err(f->adev->dev, "TLB flush failed for PASID %d.\n",
			f->pasid);
		dma_fence_set_error(&f->base, r);
	}

	dma_fence_signal(&f->base);
	dma_fence_put(&f->base);
}

static const struct dma_fence_ops amdgpu_tlb_fence_ops = {
	.get_driver_name = amdgpu_tlb_fence_get_driver_name,
	.get_timeline_name = amdgpu_tlb_fence_get_timeline_name
};

void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm,
				struct dma_fence **fence)
{
	struct amdgpu_tlb_fence *f;

	f = kmalloc_obj(*f);
	if (!f) {
		/*
		 * We can't fail since the PDEs and PTEs are already updated, so
		 * just block for the dependency and execute the TLB flush
		 */
		if (*fence)
			dma_fence_wait(*fence, false);

		amdgpu_gmc_flush_gpu_tlb_pasid(adev, vm->pasid, 2, true, 0);
		*fence = dma_fence_get_stub();
		return;
	}

	f->adev = adev;
	f->dependency = *fence;
	f->pasid = vm->pasid;
	INIT_WORK(&f->work, amdgpu_tlb_fence_work);
	spin_lock_init(&f->lock);

	dma_fence_init64(&f->base, &amdgpu_tlb_fence_ops, &f->lock,
			 vm->tlb_fence_context, atomic64_read(&vm->tlb_seq));

	/* TODO: We probably need a separate wq here */
	dma_fence_get(&f->base);
	schedule_work(&f->work);

	*fence = &f->base;
}

Annotation

Implementation Notes