drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h- Extension
.h- Size
- 16826 bytes
- Lines
- 541
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct amd_sriov_msg_init_data_headerstruct amd_sriov_msg_uuid_infostruct amd_sriov_msg_pf2vf_info_headerstruct amd_sriov_msg_pf2vf_infostruct amd_sriov_msg_vf2pf_info_headerstruct amd_sriov_msg_vf2pf_infostruct amd_sriov_ras_telemetry_headerstruct amd_sriov_ras_telemetry_error_countstruct amd_sriov_ras_cper_dumpstruct amd_sriov_ras_chk_critistruct amd_sriov_uniras_shared_memstruct amdsriov_ras_telemetryenum amd_sriov_crit_region_versionenum amd_sriov_msg_table_id_enumenum amd_sriov_ucode_engine_idenum amd_sriov_mailbox_request_messageenum amd_sriov_mailbox_response_messageenum amd_sriov_ras_telemetry_gpu_blockenum amd_sriov_gpu_init_data_version
Annotated Snippet
struct amd_sriov_msg_init_data_header {
char signature[4]; /* "INDA" */
uint32_t version;
uint32_t checksum;
uint32_t initdata_offset; /* 0 */
uint32_t initdata_size_in_kb; /* 5MB */
uint32_t valid_tables;
uint32_t vbios_img_offset;
uint32_t vbios_img_size_in_kb;
uint32_t dataexchange_offset;
uint32_t dataexchange_size_in_kb;
uint32_t ras_tele_info_offset;
uint32_t ras_tele_info_size_in_kb;
uint32_t ip_discovery_offset;
uint32_t ip_discovery_size_in_kb;
uint32_t bad_page_info_offset;
uint32_t bad_page_size_in_kb;
uint32_t reserved[8];
};
/*
* PF2VF history log:
* v1 defined in amdgim
* v2 current
*
* VF2PF history log:
* v1 defined in amdgim
* v2 defined in amdgim
* v3 current
*/
#define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER 2
#define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER 3
#define AMD_SRIOV_MSG_RESERVE_UCODE 24
#define AMD_SRIOV_MSG_RESERVE_VCN_INST 4
enum amd_sriov_ucode_engine_id {
AMD_SRIOV_UCODE_ID_VCE = 0,
AMD_SRIOV_UCODE_ID_UVD,
AMD_SRIOV_UCODE_ID_MC,
AMD_SRIOV_UCODE_ID_ME,
AMD_SRIOV_UCODE_ID_PFP,
AMD_SRIOV_UCODE_ID_CE,
AMD_SRIOV_UCODE_ID_RLC,
AMD_SRIOV_UCODE_ID_RLC_SRLC,
AMD_SRIOV_UCODE_ID_RLC_SRLG,
AMD_SRIOV_UCODE_ID_RLC_SRLS,
AMD_SRIOV_UCODE_ID_MEC,
AMD_SRIOV_UCODE_ID_MEC2,
AMD_SRIOV_UCODE_ID_SOS,
AMD_SRIOV_UCODE_ID_ASD,
AMD_SRIOV_UCODE_ID_TA_RAS,
AMD_SRIOV_UCODE_ID_TA_XGMI,
AMD_SRIOV_UCODE_ID_SMC,
AMD_SRIOV_UCODE_ID_SDMA,
AMD_SRIOV_UCODE_ID_SDMA2,
AMD_SRIOV_UCODE_ID_VCN,
AMD_SRIOV_UCODE_ID_DMCU,
AMD_SRIOV_UCODE_ID__MAX
};
#pragma pack(push, 1) // PF2VF / VF2PF data areas are byte packed
union amd_sriov_msg_feature_flags {
struct {
uint32_t error_log_collect : 1;
uint32_t host_load_ucodes : 1;
uint32_t host_flr_vramlost : 1;
uint32_t mm_bw_management : 1;
uint32_t pp_one_vf_mode : 1;
uint32_t reg_indirect_acc : 1;
uint32_t av1_support : 1;
uint32_t vcn_rb_decouple : 1;
uint32_t mes_info_dump_enable : 1;
uint32_t ras_caps : 1;
uint32_t ras_telemetry : 1;
uint32_t ras_cper : 1;
uint32_t xgmi_ta_ext_peer_link : 1;
uint32_t xgmi_connected_to_cpu : 1;
uint32_t ptl_support : 1;
uint32_t unitid_support : 1;
uint32_t reserved : 16;
} flags;
uint32_t all;
};
union amd_sriov_reg_access_flags {
struct {
uint32_t vf_reg_access_ih : 1;
Annotation
- Detected declarations: `struct amd_sriov_msg_init_data_header`, `struct amd_sriov_msg_uuid_info`, `struct amd_sriov_msg_pf2vf_info_header`, `struct amd_sriov_msg_pf2vf_info`, `struct amd_sriov_msg_vf2pf_info_header`, `struct amd_sriov_msg_vf2pf_info`, `struct amd_sriov_ras_telemetry_header`, `struct amd_sriov_ras_telemetry_error_count`, `struct amd_sriov_ras_cper_dump`, `struct amd_sriov_ras_chk_criti`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.