drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c- Extension
.c- Size
- 112173 bytes
- Lines
- 3565
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/pci.hdrm/drm_edid.hdrm/drm_fourcc.hdrm/drm_modeset_helper.hdrm/drm_modeset_helper_vtables.hdrm/drm_vblank.hamdgpu.hamdgpu_pm.hamdgpu_i2c.hatom.hamdgpu_atombios.hatombios_crtc.hatombios_encoders.hamdgpu_pll.hamdgpu_connectors.hamdgpu_display.hdce_v6_0.hsid.hbif/bif_3_0_d.hbif/bif_3_0_sh_mask.hoss/oss_1_0_d.hoss/oss_1_0_sh_mask.hgca/gfx_6_0_d.hgca/gfx_6_0_sh_mask.hgca/gfx_7_2_enum.hgmc/gmc_6_0_d.hgmc/gmc_6_0_sh_mask.hdce/dce_6_0_d.hdce/dce_6_0_sh_mask.hsi_enums.h
Detected Declarations
struct dce6_wm_paramsfunction dce_v6_0_audio_endpt_rregfunction dce_v6_0_audio_endpt_wregfunction dce_v6_0_vblank_get_counterfunction dce_v6_0_pageflip_interrupt_initfunction dce_v6_0_pageflip_interrupt_finifunction pageflipfunction dce_v6_0_crtc_get_scanoutposfunction connectedfunction pinfunction dce_v6_0_hpd_int_ackfunction cardfunction cardfunction dce_v6_0_hpd_get_gpio_regfunction dce_v6_0_is_display_hungfunction dce_v6_0_set_vga_render_statefunction dce_v6_0_get_num_crtcfunction dce_v6_0_disable_dcefunction dce_v6_0_program_fmtfunction channelsfunction bandwidthfunction displayfunction displayfunction displayfunction displayfunction displayfunction watermarkfunction bandwidthfunction bandwidthfunction hidingfunction controllerfunction controllerfunction allocationfunction dce_v6_0_audio_get_connected_pinsfunction dce_v6_0_audio_select_pinfunction dce_v6_0_audio_write_latency_fieldsfunction dce_v6_0_audio_write_speaker_allocationfunction dce_v6_0_audio_write_sad_regsfunction dce_v6_0_audio_enablefunction dce_v6_0_audio_initfunction dce_v6_0_audio_finifunction dce_v6_0_audio_set_vbi_packetfunction dce_v6_0_audio_set_acrfunction dce_v6_0_audio_set_avi_infoframefunction dce_v6_0_audio_set_dtofunction dce_v6_0_audio_set_packetfunction dce_v6_0_audio_set_mutefunction dce_v6_0_audio_hdmi_enable
Annotated Snippet
struct dce6_wm_params {
u32 dram_channels; /* number of dram channels */
u32 yclk; /* bandwidth per dram data pin in kHz */
u32 sclk; /* engine clock in kHz */
u32 disp_clk; /* display clock in kHz */
u32 src_width; /* viewport width */
u32 active_time; /* active display time in ns */
u32 blank_time; /* blank time in ns */
bool interlaced; /* mode is interlaced */
fixed20_12 vsc; /* vertical scale ratio */
u32 num_heads; /* number of active crtcs */
u32 bytes_per_pixel; /* bytes per pixel display + overlay */
u32 lb_size; /* line buffer allocated to pipe */
u32 vtaps; /* vertical scaler taps */
};
/**
* dce_v6_0_dram_bandwidth - get the dram bandwidth
*
* @wm: watermark calculation data
*
* Calculate the raw dram bandwidth (CIK).
* Used for display watermark bandwidth calculations
* Returns the dram bandwidth in MBytes/s
*/
static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
{
/* Calculate raw DRAM Bandwidth */
fixed20_12 dram_efficiency; /* 0.7 */
fixed20_12 yclk, dram_channels, bandwidth;
fixed20_12 a;
a.full = dfixed_const(1000);
yclk.full = dfixed_const(wm->yclk);
yclk.full = dfixed_div(yclk, a);
dram_channels.full = dfixed_const(wm->dram_channels * 4);
a.full = dfixed_const(10);
dram_efficiency.full = dfixed_const(7);
dram_efficiency.full = dfixed_div(dram_efficiency, a);
bandwidth.full = dfixed_mul(dram_channels, yclk);
bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
return dfixed_trunc(bandwidth);
}
/**
* dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
*
* @wm: watermark calculation data
*
* Calculate the dram bandwidth used for display (CIK).
* Used for display watermark bandwidth calculations
* Returns the dram bandwidth for display in MBytes/s
*/
static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
{
/* Calculate DRAM Bandwidth and the part allocated to display. */
fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
fixed20_12 yclk, dram_channels, bandwidth;
fixed20_12 a;
a.full = dfixed_const(1000);
yclk.full = dfixed_const(wm->yclk);
yclk.full = dfixed_div(yclk, a);
dram_channels.full = dfixed_const(wm->dram_channels * 4);
a.full = dfixed_const(10);
disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
bandwidth.full = dfixed_mul(dram_channels, yclk);
bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
return dfixed_trunc(bandwidth);
}
/**
* dce_v6_0_data_return_bandwidth - get the data return bandwidth
*
* @wm: watermark calculation data
*
* Calculate the data return bandwidth used for display (CIK).
* Used for display watermark bandwidth calculations
* Returns the data return bandwidth in MBytes/s
*/
static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
{
/* Calculate the display Data return Bandwidth */
fixed20_12 return_efficiency; /* 0.8 */
fixed20_12 sclk, bandwidth;
fixed20_12 a;
Annotation
- Immediate include surface: `linux/pci.h`, `drm/drm_edid.h`, `drm/drm_fourcc.h`, `drm/drm_modeset_helper.h`, `drm/drm_modeset_helper_vtables.h`, `drm/drm_vblank.h`, `amdgpu.h`, `amdgpu_pm.h`.
- Detected declarations: `struct dce6_wm_params`, `function dce_v6_0_audio_endpt_rreg`, `function dce_v6_0_audio_endpt_wreg`, `function dce_v6_0_vblank_get_counter`, `function dce_v6_0_pageflip_interrupt_init`, `function dce_v6_0_pageflip_interrupt_fini`, `function pageflip`, `function dce_v6_0_crtc_get_scanoutpos`, `function connected`, `function pin`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.