drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
Extension
.c
Size
128693 bytes
Lines
4177
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (adev->gfx.imu.funcs->init_microcode) {
			err = adev->gfx.imu.funcs->init_microcode(adev);
			if (err)
				dev_err(adev->dev, "Failed to load imu firmware!\n");
		}
	}

out:
	if (err) {
		amdgpu_ucode_release(&adev->gfx.rlc_fw);
		amdgpu_ucode_release(&adev->gfx.mec_fw);
	}

	return err;
}

static u32 gfx_v12_1_get_csb_size(struct amdgpu_device *adev)
{
	u32 count = 0;
	const struct cs_section_def *sect = NULL;
	const struct cs_extent_def *ext = NULL;

	count += 1;

	for (sect = gfx12_cs_data; sect->section != NULL; ++sect) {
		if (sect->id == SECT_CONTEXT) {
			for (ext = sect->section; ext->extent != NULL; ++ext)
				count += 2 + ext->reg_count;
		} else
			return 0;
	}

	return count;
}

static void gfx_v12_1_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer)
{
	u32 count = 0, clustercount = 0, i;
	const struct cs_section_def *sect = NULL;
	const struct cs_extent_def *ext = NULL;

	if (adev->gfx.rlc.cs_data == NULL)
		return;
	if (buffer == NULL)
		return;

	count += 1;

	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
		if (sect->id == SECT_CONTEXT) {
			for (ext = sect->section; ext->extent != NULL; ++ext) {
				clustercount++;
				buffer[count++] = ext->reg_count;
				buffer[count++] = ext->reg_index;

				for (i = 0; i < ext->reg_count; i++)
					buffer[count++] = cpu_to_le32(ext->extent[i]);
			}
		} else
			return;
	}

	buffer[0] = clustercount;
}

static void gfx_v12_1_rlc_fini(struct amdgpu_device *adev)
{
	/* clear state block */
	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
			&adev->gfx.rlc.clear_state_gpu_addr,
			(void **)&adev->gfx.rlc.cs_ptr);

	/* jump table block */
	amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
			&adev->gfx.rlc.cp_table_gpu_addr,
			(void **)&adev->gfx.rlc.cp_table_ptr);
}

static void gfx_v12_1_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
{
	int xcc_id, num_xcc;
	struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;

	num_xcc = NUM_XCC(adev->gfx.xcc_mask);
	for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) {
		reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)];

		reg_access_ctrl->grbm_cntl =
			SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL);
		reg_access_ctrl->grbm_idx =

Annotation

Implementation Notes