drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
Extension
.c
Size
247874 bytes
Lines
7211
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (err == -ENODEV) {
			err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
						   AMDGPU_UCODE_REQUIRED,
						   "amdgpu/%s_pfp.bin", chip_name);
		}
	} else {
		err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
					   AMDGPU_UCODE_REQUIRED,
					   "amdgpu/%s_pfp.bin", chip_name);
	}
	if (err)
		goto out;
	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
	adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
	adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);

	if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
		err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
					   AMDGPU_UCODE_OPTIONAL,
					   "amdgpu/%s_me_2.bin", chip_name);
		if (err == -ENODEV) {
			err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
						   AMDGPU_UCODE_REQUIRED,
						   "amdgpu/%s_me.bin", chip_name);
		}
	} else {
		err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
					   AMDGPU_UCODE_REQUIRED,
					   "amdgpu/%s_me.bin", chip_name);
	}
	if (err)
		goto out;
	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
	adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);

	adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);

	if (adev->asic_type >= CHIP_POLARIS10 && adev->asic_type <= CHIP_POLARIS12) {
		err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
					   AMDGPU_UCODE_OPTIONAL,
					   "amdgpu/%s_ce_2.bin", chip_name);
		if (err == -ENODEV) {
			err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
						   AMDGPU_UCODE_REQUIRED,
						   "amdgpu/%s_ce.bin", chip_name);
		}
	} else {
		err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
					   AMDGPU_UCODE_REQUIRED,
					   "amdgpu/%s_ce.bin", chip_name);
	}
	if (err)
		goto out;
	cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
	adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
	adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);

	/*
	 * Support for MCBP/Virtualization in combination with chained IBs is
	 * formal released on feature version #46
	 */
	if (adev->gfx.ce_feature_version >= 46 &&
	    adev->gfx.pfp_feature_version >= 46) {
		adev->virt.chained_ib_support = true;
		drm_info(adev_to_drm(adev), "Chained IB support enabled!\n");
	} else
		adev->virt.chained_ib_support = false;

	err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
				   AMDGPU_UCODE_REQUIRED,
				   "amdgpu/%s_rlc.bin", chip_name);
	if (err)
		goto out;
	rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
	adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
	adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);

	adev->gfx.rlc.save_and_restore_offset =
			le32_to_cpu(rlc_hdr->save_and_restore_offset);
	adev->gfx.rlc.clear_state_descriptor_offset =
			le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
	adev->gfx.rlc.avail_scratch_ram_locations =
			le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
	adev->gfx.rlc.reg_restore_list_size =
			le32_to_cpu(rlc_hdr->reg_restore_list_size);
	adev->gfx.rlc.reg_list_format_start =
			le32_to_cpu(rlc_hdr->reg_list_format_start);
	adev->gfx.rlc.reg_list_format_separate_start =
			le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
	adev->gfx.rlc.starting_offsets_start =

Annotation

Implementation Notes