drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/gfxhub_v12_1.c
Extension
.c
Size
28314 bytes
Lines
865
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (adev->gmc.pdb0_bo) {
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
				     (u32)(adev->gmc.fb_start >> 12));
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
				     (u32)(adev->gmc.fb_start >> 44));

			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
				     (u32)(adev->gmc.gart_end >> 12));
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
				     (u32)(adev->gmc.gart_end >> 44));
		} else {
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
				     (u32)(adev->gmc.gart_start >> 12));
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
				     (u32)(adev->gmc.gart_start >> 44));

			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
				     (u32)(adev->gmc.gart_end >> 12));
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
				     (u32)(adev->gmc.gart_end >> 44));
		}
	}
}

static void gfxhub_v12_1_xcc_init_system_aperture_regs(struct amdgpu_device *adev,
						       uint32_t xcc_mask)
{
	uint64_t value;
	uint32_t tmp;
	int i;

	/*TODO: revisit whether the SRIOV guest access to theseregisters
	 * is blocked by security policy or not */
	if (amdgpu_sriov_vf(adev))
		return;

	for_each_inst(i, xcc_mask) {
		if (adev->gmc.pdb0_bo) {
			/* Disable agp and system aperture
			 * when vmid0 page table is enabled */
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_FB_LOCATION_TOP_LO32, 0);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_FB_LOCATION_TOP_HI32, 0);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_FB_LOCATION_BASE_LO32,
				     0xFFFFFFFF);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_FB_LOCATION_BASE_HI32, 1);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_AGP_TOP_LO32, 0);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_AGP_TOP_HI32, 0);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_AGP_BOT_LO32,
				     0xFFFFFFFF);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_AGP_BOT_HI32, 1);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_LO32,
				     0xFFFFFFFF);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_SYSTEM_APERTURE_LOW_ADDR_HI32,
				     0x7F);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_LO32, 0);
			WREG32_SOC15(GC, GET_INST(GC, i),
				     regGCMC_VM_SYSTEM_APERTURE_HIGH_ADDR_HI32, 0);
		} else {
			/* Program the AGP BAR */
			WREG32_SOC15_RLC(GC, GET_INST(GC, i),
					 regGCMC_VM_AGP_BASE_LO32, 0);
			WREG32_SOC15_RLC(GC, GET_INST(GC, i),
					 regGCMC_VM_AGP_BASE_HI32, 0);
			WREG32_SOC15_RLC(GC, GET_INST(GC, i),
					 regGCMC_VM_AGP_BOT_LO32,
					 lower_32_bits(adev->gmc.agp_start >> 24));
			WREG32_SOC15_RLC(GC, GET_INST(GC, i),
					 regGCMC_VM_AGP_BOT_HI32,
					 upper_32_bits(adev->gmc.agp_start >> 24));
			WREG32_SOC15_RLC(GC, GET_INST(GC, i),
					 regGCMC_VM_AGP_TOP_LO32,

Annotation

Implementation Notes