drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/imu_v12_0.c- Extension
.c- Size
- 17260 bytes
- Lines
- 407
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/firmware.hamdgpu.hamdgpu_imu.hamdgpu_dpm.himu_v12_0.hgc/gc_12_0_0_offset.hgc/gc_12_0_0_sh_mask.hmmhub/mmhub_4_1_0_offset.h
Detected Declarations
function imu_v12_0_init_microcodefunction imu_v12_0_load_microcodefunction imu_v12_0_wait_for_reset_statusfunction imu_v12_0_setupfunction imu_v12_0_startfunction program_imu_rlc_ram_oldfunction imu_v12_0_grbm_gfx_index_remapfunction imu_v12_init_gfxhub_settingsfunction program_imu_rlc_ramfunction imu_v12_0_program_rlc_ram
Annotated Snippet
if (reg == SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX)) {
val_l = imu_v12_0_grbm_gfx_index_remap(adev, data, false);
val_h = imu_v12_0_grbm_gfx_index_remap(adev, data, true);
} else {
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, val_h);
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, reg | val_l);
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, data);
}
}
}
static void imu_v12_0_program_rlc_ram(struct amdgpu_device *adev)
{
u32 reg_data, size = 0;
const u32 *data = NULL;
int r = -EINVAL;
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2);
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
case IP_VERSION(12, 0, 0):
case IP_VERSION(12, 0, 1):
if (!r)
program_imu_rlc_ram(adev, data, (const u32)size);
else
program_imu_rlc_ram_old(adev, imu_rlc_ram_golden_12_0_1,
(const u32)ARRAY_SIZE(imu_rlc_ram_golden_12_0_1));
break;
default:
BUG();
break;
}
//Indicate the latest entry
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_HIGH, 0);
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_ADDR_LOW, 0);
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_DATA, 0);
reg_data = RREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX);
reg_data |= GFX_IMU_RLC_RAM_INDEX__RAM_VALID_MASK;
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, reg_data);
}
const struct amdgpu_imu_funcs gfx_v12_0_imu_funcs = {
.init_microcode = imu_v12_0_init_microcode,
.load_microcode = imu_v12_0_load_microcode,
.setup_imu = imu_v12_0_setup,
.start_imu = imu_v12_0_start,
.program_rlc_ram = imu_v12_0_program_rlc_ram,
.wait_for_reset_status = imu_v12_0_wait_for_reset_status,
};
Annotation
- Immediate include surface: `linux/firmware.h`, `amdgpu.h`, `amdgpu_imu.h`, `amdgpu_dpm.h`, `imu_v12_0.h`, `gc/gc_12_0_0_offset.h`, `gc/gc_12_0_0_sh_mask.h`, `mmhub/mmhub_4_1_0_offset.h`.
- Detected declarations: `function imu_v12_0_init_microcode`, `function imu_v12_0_load_microcode`, `function imu_v12_0_wait_for_reset_status`, `function imu_v12_0_setup`, `function imu_v12_0_start`, `function program_imu_rlc_ram_old`, `function imu_v12_0_grbm_gfx_index_remap`, `function imu_v12_init_gfxhub_settings`, `function program_imu_rlc_ram`, `function imu_v12_0_program_rlc_ram`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.