drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c- Extension
.c- Size
- 20659 bytes
- Lines
- 735
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu.hamdgpu_jpeg.hamdgpu_pm.hsoc15.hsoc15d.hjpeg_v2_0.hjpeg_v4_0_3.hvcn/vcn_5_0_0_offset.hvcn/vcn_5_0_0_sh_mask.hivsrcid/vcn/irqsrcs_vcn_5_0.hjpeg_v5_0_0.h
Detected Declarations
function jpeg_v5_0_0_early_initfunction jpeg_v5_0_0_sw_initfunction jpeg_v5_0_0_sw_finifunction jpeg_v5_0_0_hw_initfunction jpeg_v5_0_0_hw_finifunction jpeg_v5_0_0_suspendfunction jpeg_v5_0_0_resumefunction jpeg_v5_0_0_disable_clock_gatingfunction jpeg_v5_0_0_enable_clock_gatingfunction jpeg_v5_0_0_disable_power_gatingfunction jpeg_v5_0_0_enable_power_gatingfunction jpeg_engine_5_0_0_dpg_clock_gating_modefunction jpeg_v5_0_0_start_dpg_modefunction jpeg_v5_0_0_stop_dpg_modefunction jpeg_v5_0_0_startfunction jpeg_v5_0_0_stopfunction jpeg_v5_0_0_dec_ring_get_rptrfunction jpeg_v5_0_0_dec_ring_get_wptrfunction jpeg_v5_0_0_dec_ring_set_wptrfunction jpeg_v5_0_0_is_idlefunction jpeg_v5_0_0_wait_for_idlefunction jpeg_v5_0_0_set_clockgating_statefunction jpeg_v5_0_0_set_powergating_statefunction jpeg_v5_0_0_set_interrupt_statefunction jpeg_v5_0_0_process_interruptfunction jpeg_v5_0_0_ring_resetfunction jpeg_v5_0_0_set_dec_ring_funcsfunction jpeg_v5_0_0_set_irq_funcs
Annotated Snippet
#include "amdgpu.h"
#include "amdgpu_jpeg.h"
#include "amdgpu_pm.h"
#include "soc15.h"
#include "soc15d.h"
#include "jpeg_v2_0.h"
#include "jpeg_v4_0_3.h"
#include "vcn/vcn_5_0_0_offset.h"
#include "vcn/vcn_5_0_0_sh_mask.h"
#include "ivsrcid/vcn/irqsrcs_vcn_5_0.h"
#include "jpeg_v5_0_0.h"
static const struct amdgpu_hwip_reg_entry jpeg_reg_list_5_0[] = {
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_POWER_STATUS),
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_INT_STAT),
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_RPTR),
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_WPTR),
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_CNTL),
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_RB_SIZE),
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JRBC_STATUS),
SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_ADDR_MODE),
SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG),
SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_Y_GFX10_TILING_SURFACE),
SOC15_REG_ENTRY_STR(JPEG, 0, regJPEG_DEC_UV_GFX10_TILING_SURFACE),
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_PITCH),
SOC15_REG_ENTRY_STR(JPEG, 0, regUVD_JPEG_UV_PITCH),
};
static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
static int jpeg_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
enum amd_powergating_state state);
/**
* jpeg_v5_0_0_early_init - set function pointers
*
* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
*
* Set ring and irq function pointers
*/
static int jpeg_v5_0_0_early_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
adev->jpeg.num_jpeg_inst = 1;
adev->jpeg.num_jpeg_rings = 1;
jpeg_v5_0_0_set_dec_ring_funcs(adev);
jpeg_v5_0_0_set_irq_funcs(adev);
return 0;
}
/**
* jpeg_v5_0_0_sw_init - sw init for JPEG block
*
* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
*
* Load firmware and sw initialization
*/
static int jpeg_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
int r;
/* JPEG TRAP */
r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
VCN_5_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
if (r)
return r;
r = amdgpu_jpeg_sw_init(adev);
if (r)
return r;
r = amdgpu_jpeg_resume(adev);
if (r)
return r;
ring = adev->jpeg.inst->ring_dec;
ring->use_doorbell = true;
ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
ring->vm_hub = AMDGPU_MMHUB0(0);
sprintf(ring->name, "jpeg_dec");
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
AMDGPU_RING_PRIO_DEFAULT, NULL);
if (r)
Annotation
- Immediate include surface: `amdgpu.h`, `amdgpu_jpeg.h`, `amdgpu_pm.h`, `soc15.h`, `soc15d.h`, `jpeg_v2_0.h`, `jpeg_v4_0_3.h`, `vcn/vcn_5_0_0_offset.h`.
- Detected declarations: `function jpeg_v5_0_0_early_init`, `function jpeg_v5_0_0_sw_init`, `function jpeg_v5_0_0_sw_fini`, `function jpeg_v5_0_0_hw_init`, `function jpeg_v5_0_0_hw_fini`, `function jpeg_v5_0_0_suspend`, `function jpeg_v5_0_0_resume`, `function jpeg_v5_0_0_disable_clock_gating`, `function jpeg_v5_0_0_enable_clock_gating`, `function jpeg_v5_0_0_disable_power_gating`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.