drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_1.c- Extension
.c- Size
- 32661 bytes
- Lines
- 1112
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
amdgpu.hamdgpu_jpeg.hamdgpu_pm.hsoc15.hsoc15d.hjpeg_v4_0_3.hjpeg_v5_0_1.hmmsch_v5_0.hvcn/vcn_5_0_0_offset.hvcn/vcn_5_0_0_sh_mask.hivsrcid/vcn/irqsrcs_vcn_5_0.h
Detected Declarations
function jpeg_v5_0_1_core_reg_offsetfunction jpeg_v5_0_1_early_initfunction jpeg_v5_0_1_sw_initfunction jpeg_v5_0_1_sw_finifunction jpeg_v5_0_1_hw_initfunction jpeg_v5_0_1_hw_finifunction jpeg_v5_0_1_suspendfunction jpeg_v5_0_1_resumefunction jpeg_v5_0_1_init_instfunction jpeg_v5_0_1_deinit_instfunction jpeg_v5_0_1_init_jrbcfunction jpeg_v5_0_1_start_sriovfunction jpeg_v5_0_1_startfunction jpeg_v5_0_1_stopfunction jpeg_v5_0_1_dec_ring_get_rptrfunction jpeg_v5_0_1_dec_ring_get_wptrfunction jpeg_v5_0_1_dec_ring_set_wptrfunction jpeg_v5_0_1_is_idlefunction jpeg_v5_0_1_wait_for_idlefunction jpeg_v5_0_1_set_clockgating_statefunction jpeg_v5_0_1_set_powergating_statefunction jpeg_v5_0_1_set_interrupt_statefunction jpeg_v5_0_1_set_ras_interrupt_statefunction jpeg_v5_0_1_process_interruptfunction jpeg_v5_0_1_core_stall_resetfunction jpeg_v5_0_1_ring_resetfunction jpeg_v5_0_1_set_dec_ring_funcsfunction jpeg_v5_0_1_set_irq_funcsfunction jpeg_v5_0_1_query_poison_by_instancefunction jpeg_v5_0_1_query_ras_poison_statusfunction jpeg_v5_0_1_aca_bank_parserfunction jpeg_v5_0_1_aca_bank_is_validfunction jpeg_v5_0_1_ras_late_initfunction jpeg_v5_0_1_set_ras_funcs
Annotated Snippet
if (!amdgpu_sriov_vf(adev)) {
ring->doorbell_index =
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
1 + j + 11 * jpeg_inst;
} else {
ring->doorbell_index =
(adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
2 + j + 32 * jpeg_inst;
}
sprintf(ring->name, "jpeg_dec_%d.%d", adev->jpeg.inst[i].aid_id, j);
r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
AMDGPU_RING_PRIO_DEFAULT, NULL);
if (r)
return r;
adev->jpeg.internal.jpeg_pitch[j] =
regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET;
adev->jpeg.inst[i].external.jpeg_pitch[j] =
SOC15_REG_OFFSET1(JPEG, jpeg_inst, regUVD_JRBC_SCRATCH0,
(j ? jpeg_v5_0_1_core_reg_offset(j) : 0));
}
}
if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__JPEG)) {
r = amdgpu_jpeg_ras_sw_init(adev);
if (r) {
dev_err(adev->dev, "Failed to initialize jpeg ras block!\n");
return r;
}
}
r = amdgpu_jpeg_reg_dump_init(adev, jpeg_reg_list_5_0_1, ARRAY_SIZE(jpeg_reg_list_5_0_1));
if (r)
return r;
adev->jpeg.supported_reset =
amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
if (!amdgpu_sriov_vf(adev))
adev->jpeg.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
return r;
}
/**
* jpeg_v5_0_1_sw_fini - sw fini for JPEG block
*
* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
*
* JPEG suspend and free up sw allocation
*/
static int jpeg_v5_0_1_sw_fini(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
int r;
r = amdgpu_jpeg_suspend(adev);
if (r)
return r;
amdgpu_jpeg_sysfs_reset_mask_fini(adev);
r = amdgpu_jpeg_sw_fini(adev);
return r;
}
/**
* jpeg_v5_0_1_hw_init - start and test JPEG block
*
* @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
*
*/
static int jpeg_v5_0_1_hw_init(struct amdgpu_ip_block *ip_block)
{
struct amdgpu_device *adev = ip_block->adev;
struct amdgpu_ring *ring;
int i, j, r, jpeg_inst;
if (amdgpu_sriov_vf(adev)) {
r = jpeg_v5_0_1_start_sriov(adev);
if (r)
return r;
for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) {
ring = &adev->jpeg.inst[i].ring_dec[j];
ring->wptr = 0;
ring->wptr_old = 0;
jpeg_v5_0_1_dec_ring_set_wptr(ring);
Annotation
- Immediate include surface: `amdgpu.h`, `amdgpu_jpeg.h`, `amdgpu_pm.h`, `soc15.h`, `soc15d.h`, `jpeg_v4_0_3.h`, `jpeg_v5_0_1.h`, `mmsch_v5_0.h`.
- Detected declarations: `function jpeg_v5_0_1_core_reg_offset`, `function jpeg_v5_0_1_early_init`, `function jpeg_v5_0_1_sw_init`, `function jpeg_v5_0_1_sw_fini`, `function jpeg_v5_0_1_hw_init`, `function jpeg_v5_0_1_hw_fini`, `function jpeg_v5_0_1_suspend`, `function jpeg_v5_0_1_resume`, `function jpeg_v5_0_1_init_inst`, `function jpeg_v5_0_1_deinit_inst`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.