drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h
Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_2.h- Extension
.h- Size
- 8366 bytes
- Lines
- 112
- Domain
- Driver Families
- Bucket
- drivers/gpu
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
enum amdgpu_jpeg_v5_0_2_sub_block
Annotated Snippet
#ifndef __JPEG_V5_0_2_H__
#define __JPEG_V5_0_2_H__
extern const struct amdgpu_ip_block_version jpeg_v5_0_2_ip_block;
#define regUVD_JRBC0_UVD_JRBC_SCRATCH0_INTERNAL_OFFSET 0x4094
#define regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET 0x1bffe
#define regUVD_JRBC0_UVD_JRBC_RB_WPTR 0x0640
#define regUVD_JRBC0_UVD_JRBC_RB_WPTR_BASE_IDX 1
#define regUVD_JRBC0_UVD_JRBC_STATUS 0x0649
#define regUVD_JRBC0_UVD_JRBC_STATUS_BASE_IDX 1
#define regUVD_JRBC0_UVD_JRBC_RB_RPTR 0x064a
#define regUVD_JRBC0_UVD_JRBC_RB_RPTR_BASE_IDX 1
#define regUVD_JRBC1_UVD_JRBC_RB_WPTR 0x0000
#define regUVD_JRBC1_UVD_JRBC_RB_WPTR_BASE_IDX 0
#define regUVD_JRBC1_UVD_JRBC_STATUS 0x0009
#define regUVD_JRBC1_UVD_JRBC_STATUS_BASE_IDX 0
#define regUVD_JRBC1_UVD_JRBC_RB_RPTR 0x000a
#define regUVD_JRBC1_UVD_JRBC_RB_RPTR_BASE_IDX 0
#define regUVD_JRBC2_UVD_JRBC_RB_WPTR 0x0040
#define regUVD_JRBC2_UVD_JRBC_RB_WPTR_BASE_IDX 0
#define regUVD_JRBC2_UVD_JRBC_STATUS 0x0049
#define regUVD_JRBC2_UVD_JRBC_STATUS_BASE_IDX 0
#define regUVD_JRBC2_UVD_JRBC_RB_RPTR 0x004a
#define regUVD_JRBC2_UVD_JRBC_RB_RPTR_BASE_IDX 0
#define regUVD_JRBC3_UVD_JRBC_RB_WPTR 0x0080
#define regUVD_JRBC3_UVD_JRBC_RB_WPTR_BASE_IDX 0
#define regUVD_JRBC3_UVD_JRBC_STATUS 0x0089
#define regUVD_JRBC3_UVD_JRBC_STATUS_BASE_IDX 0
#define regUVD_JRBC3_UVD_JRBC_RB_RPTR 0x008a
#define regUVD_JRBC3_UVD_JRBC_RB_RPTR_BASE_IDX 0
#define regUVD_JRBC4_UVD_JRBC_RB_WPTR 0x00c0
#define regUVD_JRBC4_UVD_JRBC_RB_WPTR_BASE_IDX 0
#define regUVD_JRBC4_UVD_JRBC_STATUS 0x00c9
#define regUVD_JRBC4_UVD_JRBC_STATUS_BASE_IDX 0
#define regUVD_JRBC4_UVD_JRBC_RB_RPTR 0x00ca
#define regUVD_JRBC4_UVD_JRBC_RB_RPTR_BASE_IDX 0
#define regUVD_JRBC5_UVD_JRBC_RB_WPTR 0x0100
#define regUVD_JRBC5_UVD_JRBC_RB_WPTR_BASE_IDX 0
#define regUVD_JRBC5_UVD_JRBC_STATUS 0x0109
#define regUVD_JRBC5_UVD_JRBC_STATUS_BASE_IDX 0
#define regUVD_JRBC5_UVD_JRBC_RB_RPTR 0x010a
#define regUVD_JRBC5_UVD_JRBC_RB_RPTR_BASE_IDX 0
#define regUVD_JRBC6_UVD_JRBC_RB_WPTR 0x0140
#define regUVD_JRBC6_UVD_JRBC_RB_WPTR_BASE_IDX 0
#define regUVD_JRBC6_UVD_JRBC_STATUS 0x0149
#define regUVD_JRBC6_UVD_JRBC_STATUS_BASE_IDX 0
#define regUVD_JRBC6_UVD_JRBC_RB_RPTR 0x014a
#define regUVD_JRBC6_UVD_JRBC_RB_RPTR_BASE_IDX 0
#define regUVD_JRBC7_UVD_JRBC_RB_WPTR 0x0180
#define regUVD_JRBC7_UVD_JRBC_RB_WPTR_BASE_IDX 0
#define regUVD_JRBC7_UVD_JRBC_STATUS 0x0189
#define regUVD_JRBC7_UVD_JRBC_STATUS_BASE_IDX 0
#define regUVD_JRBC7_UVD_JRBC_RB_RPTR 0x018a
#define regUVD_JRBC7_UVD_JRBC_RB_RPTR_BASE_IDX 0
#define regUVD_JRBC8_UVD_JRBC_RB_WPTR 0x01c0
#define regUVD_JRBC8_UVD_JRBC_RB_WPTR_BASE_IDX 0
#define regUVD_JRBC8_UVD_JRBC_STATUS 0x01c9
#define regUVD_JRBC8_UVD_JRBC_STATUS_BASE_IDX 0
#define regUVD_JRBC8_UVD_JRBC_RB_RPTR 0x01ca
#define regUVD_JRBC8_UVD_JRBC_RB_RPTR_BASE_IDX 0
#define regUVD_JRBC9_UVD_JRBC_RB_WPTR 0x0440
#define regUVD_JRBC9_UVD_JRBC_RB_WPTR_BASE_IDX 1
#define regUVD_JRBC9_UVD_JRBC_STATUS 0x0449
#define regUVD_JRBC9_UVD_JRBC_STATUS_BASE_IDX 1
#define regUVD_JRBC9_UVD_JRBC_RB_RPTR 0x044a
#define regUVD_JRBC9_UVD_JRBC_RB_RPTR_BASE_IDX 1
#define regUVD_JMI0_JPEG_LMI_DROP 0x0663
#define regUVD_JMI0_JPEG_LMI_DROP_BASE_IDX 1
#define regUVD_JMI0_UVD_JMI_CLIENT_STALL 0x067a
#define regUVD_JMI0_UVD_JMI_CLIENT_STALL_BASE_IDX 1
#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS 0x067b
#define regUVD_JMI0_UVD_JMI_CLIENT_CLEAN_STATUS_BASE_IDX 1
#define regJPEG_CORE_RST_CTRL 0x072e
#define regJPEG_CORE_RST_CTRL_BASE_IDX 1
#define regVCN_RRMT_CNTL 0x0940
#define regVCN_RRMT_CNTL_BASE_IDX 1
enum amdgpu_jpeg_v5_0_2_sub_block {
AMDGPU_JPEG_V5_0_2_JPEG0 = 0,
AMDGPU_JPEG_V5_0_2_JPEG1,
AMDGPU_JPEG_V5_0_2_MAX_SUB_BLOCK,
};
#endif /* __JPEG_V5_0_2_H__ */Annotation
- Detected declarations: `enum amdgpu_jpeg_v5_0_2_sub_block`.
- Atlas domain: Driver Families / drivers/gpu.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.