drivers/gpu/drm/amd/amdgpu/mca_v3_0.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/mca_v3_0.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/mca_v3_0.c
Extension
.c
Size
3273 bytes
Lines
105
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "amdgpu_ras.h"
#include "amdgpu.h"
#include "amdgpu_mca.h"

#define smnMCMP0_STATUST0 	0x03830408
#define smnMCMP1_STATUST0 	0x03b30408
#define smnMCMPIO_STATUST0 	0x0c930408


static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev,
					       void *ras_error_status)
{
	amdgpu_mca_query_ras_error_count(adev,
				         smnMCMP0_STATUST0,
				         ras_error_status);
}

static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj,
				enum amdgpu_ras_block block, uint32_t sub_block_index)
{
	if (!block_obj)
		return -EINVAL;

	if ((block_obj->ras_comm.block == block) &&
		(block_obj->ras_comm.sub_block_index == sub_block_index)) {
		return 0;
	}

	return -EINVAL;
}

static const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = {
	.query_ras_error_count = mca_v3_0_mp0_query_ras_error_count,
	.query_ras_error_address = NULL,
};

struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = {
	.ras_block = {
		.hw_ops = &mca_v3_0_mp0_hw_ops,
		.ras_block_match = mca_v3_0_ras_block_match,
	},
};

static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
					       void *ras_error_status)
{
	amdgpu_mca_query_ras_error_count(adev,
				         smnMCMP1_STATUST0,
				         ras_error_status);
}

static const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = {
	.query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
	.query_ras_error_address = NULL,
};

struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = {
	.ras_block = {
		.hw_ops = &mca_v3_0_mp1_hw_ops,
		.ras_block_match = mca_v3_0_ras_block_match,
	},
};

static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
					       void *ras_error_status)
{
	amdgpu_mca_query_ras_error_count(adev,
				         smnMCMPIO_STATUST0,
				         ras_error_status);
}

static const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = {
	.query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
	.query_ras_error_address = NULL,
};

struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = {
	.ras_block = {
		.hw_ops = &mca_v3_0_mpio_hw_ops,
		.ras_block_match = mca_v3_0_ras_block_match,
	},
};

Annotation

Implementation Notes