drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
Extension
.c
Size
30094 bytes
Lines
851
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (sec_cnt) {
			dev_info(adev->dev,
				"MMHUB SubBlock %s, SEC %d\n",
				mmhub_v1_0_ras_fields[i].name,
				sec_cnt);
			*sec_count += sec_cnt;
		}

		ded_cnt = (value &
				mmhub_v1_0_ras_fields[i].ded_count_mask) >>
				mmhub_v1_0_ras_fields[i].ded_count_shift;
		if (ded_cnt) {
			dev_info(adev->dev,
				"MMHUB SubBlock %s, DED %d\n",
				mmhub_v1_0_ras_fields[i].name,
				ded_cnt);
			*ded_count += ded_cnt;
		}
	}

	return 0;
}

static void mmhub_v1_0_query_ras_error_count(struct amdgpu_device *adev,
					   void *ras_error_status)
{
	struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
	uint32_t sec_count = 0, ded_count = 0;
	uint32_t i;
	uint32_t reg_value;

	err_data->ue_count = 0;
	err_data->ce_count = 0;

	for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++) {
		reg_value =
			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));
		if (reg_value)
			mmhub_v1_0_get_ras_error_count(adev,
				&mmhub_v1_0_edc_cnt_regs[i],
				reg_value, &sec_count, &ded_count);
	}

	err_data->ce_count += sec_count;
	err_data->ue_count += ded_count;
}

static void mmhub_v1_0_reset_ras_error_count(struct amdgpu_device *adev)
{
	uint32_t i;

	/* read back edc counter registers to reset the counters to 0 */
	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
		for (i = 0; i < ARRAY_SIZE(mmhub_v1_0_edc_cnt_regs); i++)
			RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_0_edc_cnt_regs[i]));
	}
}

struct amdgpu_ras_block_hw_ops mmhub_v1_0_ras_hw_ops = {
	.query_ras_error_count = mmhub_v1_0_query_ras_error_count,
	.reset_ras_error_count = mmhub_v1_0_reset_ras_error_count,
};

struct amdgpu_mmhub_ras mmhub_v1_0_ras = {
	.ras_block = {
		.hw_ops = &mmhub_v1_0_ras_hw_ops,
	},
};

const struct amdgpu_mmhub_funcs mmhub_v1_0_funcs = {
	.get_fb_location = mmhub_v1_0_get_fb_location,
	.init = mmhub_v1_0_init,
	.gart_enable = mmhub_v1_0_gart_enable,
	.set_fault_enable_default = mmhub_v1_0_set_fault_enable_default,
	.gart_disable = mmhub_v1_0_gart_disable,
	.set_clockgating = mmhub_v1_0_set_clockgating,
	.get_clockgating = mmhub_v1_0_get_clockgating,
	.setup_vm_pt_regs = mmhub_v1_0_setup_vm_pt_regs,
	.update_power_gating = mmhub_v1_0_update_power_gating,
};

Annotation

Implementation Notes