drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c
Extension
.c
Size
28435 bytes
Lines
872
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (adev->gmc.pdb0_bo) {
			WREG32_SOC15(MMHUB, i,
				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
				     (u32)(gart_start >> 12));
			WREG32_SOC15(MMHUB, i,
				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
				     (u32)(gart_start >> 44));

			WREG32_SOC15(MMHUB, i,
				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
				     (u32)(adev->gmc.gart_end >> 12));
			WREG32_SOC15(MMHUB, i,
				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
				     (u32)(adev->gmc.gart_end >> 44));

		} else {
			WREG32_SOC15(MMHUB, i,
				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
				     (u32)(adev->gmc.gart_start >> 12));
			WREG32_SOC15(MMHUB, i,
				     regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
				     (u32)(adev->gmc.gart_start >> 44));

			WREG32_SOC15(MMHUB, i,
				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
				     (u32)(adev->gmc.gart_end >> 12));
			WREG32_SOC15(MMHUB, i,
				     regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
				     (u32)(adev->gmc.gart_end >> 44));
		}
	}
}

static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)
{
	uint32_t tmp, inst_mask;
	uint64_t value;
	int i;

	if (amdgpu_sriov_vf(adev))
		return;

	inst_mask = adev->aid_mask;
	for_each_inst(i, inst_mask) {
		/* Program the AGP BAR */
		WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BASE, 0);
		WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT,
			     adev->gmc.agp_start >> 24);
		WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP,
			     adev->gmc.agp_end >> 24);

		/* Program the system aperture low logical page number. */
		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
			min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);

		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
			max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);

		/* In the case squeezing vram into GART aperture, we don't use
		 * FB aperture and AGP aperture. Disable them.
		 */
		if (adev->gmc.pdb0_bo) {
			WREG32_SOC15(MMHUB, i, regMC_VM_AGP_BOT, 0xFFFFFF);
			WREG32_SOC15(MMHUB, i, regMC_VM_AGP_TOP, 0);
			WREG32_SOC15(MMHUB, i, regMC_VM_FB_LOCATION_TOP, 0);
			WREG32_SOC15(MMHUB, i, regMC_VM_FB_LOCATION_BASE,
				     0x00FFFFFF);
			WREG32_SOC15(MMHUB, i,
				     regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
				     0x3FFFFFFF);
			WREG32_SOC15(MMHUB, i,
				     regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
		}

		/* Set default page address. */
		value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
			     (u32)(value >> 12));
		WREG32_SOC15(MMHUB, i, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
			     (u32)(value >> 44));

		/* Program "protection fault". */
		WREG32_SOC15(MMHUB, i,
			     regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
			     (u32)(adev->dummy_page_addr >> 12));
		WREG32_SOC15(MMHUB, i,
			     regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
			     (u32)((u64)adev->dummy_page_addr >> 44));

		tmp = RREG32_SOC15(MMHUB, i, regVM_L2_PROTECTION_FAULT_CNTL2);

Annotation

Implementation Notes