drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

Source file repositories/reference/linux-study-clean/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c

File Facts

System
Linux kernel
Corpus path
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.c
Extension
.c
Size
20773 bytes
Lines
593
Domain
Driver Families
Bucket
drivers/gpu
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#include "amdgpu.h"
#include "mmhub_v3_0_1.h"

#include "mmhub/mmhub_3_0_1_offset.h"
#include "mmhub/mmhub_3_0_1_sh_mask.h"
#include "navi10_enum.h"

#include "soc15_common.h"

#define regMMVM_L2_CNTL3_DEFAULT				0x80100007
#define regMMVM_L2_CNTL4_DEFAULT				0x000000c1
#define regMMVM_L2_CNTL5_DEFAULT				0x00003fe0

static const char *mmhub_client_ids_v3_0_1[][2] = {
	[0][0] = "VMC",
	[1][0] = "ISPXT",
	[2][0] = "ISPIXT",
	[4][0] = "DCEDMC",
	[5][0] = "DCEVGA",
	[6][0] = "MP0",
	[7][0] = "MP1",
	[8][0] = "MPM",
	[12][0] = "ISPTNR",
	[14][0] = "ISPCRD0",
	[15][0] = "ISPCRD1",
	[16][0] = "ISPCRD2",
	[22][0] = "HDP",
	[23][0] = "LSDMA",
	[24][0] = "JPEG",
	[27][0] = "VSCH",
	[28][0] = "VCNU",
	[29][0] = "VCN",
	[1][1] = "ISPXT",
	[2][1] = "ISPIXT",
	[3][1] = "DCEDWB",
	[4][1] = "DCEDMC",
	[5][1] = "DCEVGA",
	[6][1] = "MP0",
	[7][1] = "MP1",
	[8][1] = "MPM",
	[10][1] = "ISPMWR0",
	[11][1] = "ISPMWR1",
	[12][1] = "ISPTNR",
	[13][1] = "ISPSWR",
	[14][1] = "ISPCWR0",
	[15][1] = "ISPCWR1",
	[16][1] = "ISPCWR2",
	[17][1] = "ISPCWR3",
	[18][1] = "XDP",
	[21][1] = "OSSSYS",
	[22][1] = "HDP",
	[23][1] = "LSDMA",
	[24][1] = "JPEG",
	[27][1] = "VSCH",
	[28][1] = "VCNU",
	[29][1] = "VCN",
};

static uint32_t mmhub_v3_0_1_get_invalidate_req(unsigned int vmid,
						uint32_t flush_type)
{
	u32 req = 0;

	/* invalidate using legacy mode on vmid*/
	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
			    PER_VMID_INVALIDATE_REQ, 1 << vmid);
	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
	req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
			    CLEAR_PROTECTION_FAULT_STATUS_ADDR,	0);

	return req;
}

static void
mmhub_v3_0_1_print_l2_protection_fault_status(struct amdgpu_device *adev,
					      uint32_t status)
{
	uint32_t cid, rw;
	const char *mmhub_cid;

	cid = REG_GET_FIELD(status,
			    MMVM_L2_PROTECTION_FAULT_STATUS, CID);
	rw = REG_GET_FIELD(status,
			   MMVM_L2_PROTECTION_FAULT_STATUS, RW);

Annotation

Implementation Notes